公开(公告)号：US11195915B2

公开(公告)日：2021-12-07

申请号：US16384700

申请日：2019-04-15

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian Lin ,  Frank Alexander Baiocchi ,  Seetharaman Sridhar

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423

Abstract: In some examples, a semiconductor device, comprises a semiconductor substrate; an epitaxial layer having a top side disposed on the semiconductor substrate, wherein the epitaxial layer has a source implant region, a drain implant region, a first doped region, and a second doped region, wherein the first doped region is adjacent to the source implant region and the second doped region is adjacent to the drain implant region, wherein the top side has a sloped surface over the second doped region; a gate electrode supported by the top side; a source electrode in contact with the source implant region; and a drain electrode in contact with the drain implant region.

公开(公告)号：US10581426B1

公开(公告)日：2020-03-03

申请号：US16297963

申请日：2019-03-11

Applicant: Texas Instruments Incorporated

Inventor： Haian Lin ,  Frank Alexander Baiocchi ,  Masahiko Higashi ,  Namiko Hagane

IPC: G05F1/00 ,  H02M3/335 ,  H03K17/14 ,  H01L25/16 ,  H01L21/8249 ,  H01L27/06

Abstract: An electronic device includes a first semiconductor die with a first FET having a drain connected to a switching node, a source connected to a reference node, and a gate connected to a first switch control node. The first die also includes a diode-connected bipolar transistor that forms a temperature diode next to the first FET. The temperature diode includes a cathode connected to the reference node, and an anode connected to a bias node. The electronic device also includes a second semiconductor die with a second FET, and a package structure that encloses the first and second semiconductor dies.

公开(公告)号：US10529706B2

公开(公告)日：2020-01-07

申请号：US16392476

申请日：2019-04-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian Lin ,  Frank Baiocchi

IPC: H01L23/62 ,  H01L27/02 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/36 ,  H01L29/78 ,  H01L29/861

Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.

公开(公告)号：US20190259745A1

公开(公告)日：2019-08-22

申请号：US16392476

申请日：2019-04-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian Lin ,  Frank Baiocchi

IPC: H01L27/02 ,  H01L29/417 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/861 ,  H01L29/40 ,  H01L29/36 ,  H01L29/78

Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.

公开(公告)号：US20180331083A1

公开(公告)日：2018-11-15

申请号：US16027031

申请日：2018-07-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jonathan Almeria Noquil ,  Osvaldo Jorge Lopez ,  Haian Lin

IPC: H01L25/16 ,  H01L21/56 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00 ,  H02M3/155 ,  H01L21/768 ,  H02M3/158

CPC classification number: H01L25/16 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73251 ,  H01L2224/80001 ,  H01L2224/9222 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/1425 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H02M3/155 ,  H02M3/158 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.

公开(公告)号：US10050025B2

公开(公告)日：2018-08-14

申请号：US15019275

申请日：2016-02-09

Applicant: Texas Instruments Incorporated

Inventor： Jonathan Almeria Noquil ,  Osvaldo Jorge Lopez ,  Haian Lin

IPC: H01L23/495 ,  H01L25/16 ,  H01L23/00 ,  H01L25/07 ,  H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H02M3/155 ,  H01L21/768 ,  H02M3/158

Abstract: A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.

公开(公告)号：US11616137B2

公开(公告)日：2023-03-28

申请号：US16821165

申请日：2020-03-17

Applicant: Texas Instruments Incorporated

Inventor： Haian Lin ,  Shuming Xu ,  Jacek Korec

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/47 ,  H01L29/872 ,  H01L29/417 ,  H01L29/10

Abstract: A semiconductor device containing a vertical power MOSFET with a planar gate and an integrated Schottky diode is formed by forming a source electrode on an extended drain of the vertical power MOSFET to form the Schottky diode and forming the source electrode on a source region of the vertical power MOSFET. The Schottky diode is connected through the source electrode to the source region. A drain electrode is formed at a bottom of a substrate of the semiconductor device. The Schottky diode is connected through the extended drain of the vertical power MOSFET to the drain electrode.

公开(公告)号：US20200295748A1

公开(公告)日：2020-09-17

申请号：US16794275

申请日：2020-02-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Haian Lin ,  Frank Alexander Baiocchi ,  Masahiko Higashi ,  Namiko Hagane

IPC: H03K17/14 ,  H01L25/16 ,  H01L21/8249 ,  H01L27/06

Abstract: A device includes an epitaxial layer located over a semiconductor substrate, the epitaxial layer and the substrate both having a first conductivity type. A field-effect transistor (FET) includes source and drain regions having an opposite second conductivity type disposed in the epitaxial layer, and a gate structure over the substrate and between the source and drain regions. A diode includes first and second p-type regions and an n-type region all disposed in the epitaxial layer, the n-type region touching the first p-type region. A conductive plug electrically connects the first p-type region to the source region via the substrate.

公开(公告)号：US10746890B2

公开(公告)日：2020-08-18

申请号：US16101867

申请日：2018-08-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Furen Lin ,  Frank Baiocchi ,  Haian Lin ,  Yunlong Liu ,  Lark Liu ,  Wei Song ,  ZiQiang Zhao

IPC: H01L29/417 ,  G01V1/38 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  G01V1/16 ,  G01V1/18 ,  G01V1/24 ,  H01L29/423

Abstract: A method of forming an electronic device includes forming a plurality of closed loops over a semiconductor substrate. Each closed loop has a first and a second polysilicon gate structure joined at first and second ends. Each closed loop includes an inner portion and an end portion. In the inner portion the first polysilicon gate structure runs about parallel to the second polysilicon gate structure. In the outer portion the first polysilicon gate structure converges with the second polysilicon gate structure. The method further includes forming a plurality of trench contacts. Each of the trench contacts is located between a respective pair of closed loops, passes through an epitaxial layer and contacts the substrate. The length of the trench contacts is no greater than the length of the inner portions.

公开(公告)号：US20170229435A1

公开(公告)日：2017-08-10

申请号：US15019275

申请日：2016-02-09

Applicant: Texas Instruments Incorporated

Inventor： Jonathan Almeria Noquil ,  Osvaldo Jorge Lopez ,  Haian Lin

IPC: H01L25/16 ,  H01L27/088 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L23/48

CPC classification number: H01L25/16 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73251 ,  H01L2224/80001 ,  H01L2224/9222 ,  H01L2924/00014 ,  H01L2924/1306 ,  H01L2924/1425 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H02M3/155 ,  H02M3/158 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.