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    Integrated circuit, LDMOS with bottom gate and ballast drift
    1.
    发明授权
    Integrated circuit, LDMOS with bottom gate and ballast drift 有权

    公开(公告)号：US10910472B2

    公开(公告)日：2021-02-02

    申请号：US16729824

    申请日：2019-12-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jun Cai

    IPC: H01L29/08 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L21/761

    Abstract: Disclosed examples include LDMOS transistors and integrated circuits with a gate, a body region implanted in the substrate to provide a channel region under a portion of the gate, a source adjacent the channel region, a drain laterally spaced from a first side of the gate, a drift region including a first highly doped drift region portion, a low doped gap drift region above the first highly doped drift region portion, and a second highly doped region portion above the gap drift region, and an isolation structure extending through the second highly doped region portion into the gap drift region portion, with a first end proximate the drain region and a second end under the gate dielectric layer, where the body region includes a tapered side laterally spaced from the second end of the isolation structure to define a trapezoidal JFET region.

    Transistors having gates with a lift-up region
    4.
    发明授权
    Transistors having gates with a lift-up region 有权

    公开(公告)号：US10998409B2

    公开(公告)日：2021-05-04

    申请号：US16566924

    申请日：2019-09-11

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Jun Cai

    IPC: H01L29/40 ,  H01L29/78 ,  H01L29/10 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L21/32

    Abstract: An integrated circuit includes a Laterally Diffused MOSFET (LD-MOSFET) located over a semiconductor substrate. The LD-MOSFET transistor includes a dielectric filled trench at a surface of the semiconductor substrate, and a doped region of the semiconductor substrate adjacent the dielectric-filled trench. The doped region and the dielectric-filled trench share an interface that has a terminus at the surface of the semiconductor substrate. An oxide layer is located over the semiconductor substrate, including along a surface of the doped region and along a surface of the dielectric-filled trench. The oxide layer has a first thickness over the dielectric-filled trench and a second greater thickness over the doped region.

    Zener-triggered transistor with vertically integrated Zener diode
    5.
    发明授权
    Zener-triggered transistor with vertically integrated Zener diode 有权

    公开(公告)号：US10978443B2

    公开(公告)日：2021-04-13

    申请号：US16433632

    申请日：2019-06-06

    Applicant: Texas Instruments Incorporated

    Inventor： Akram Ali Salman ,  Jun Cai ,  Krishna Praveen Mysore Rajagopal

    IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/8222 ,  H01L21/266 ,  H01L21/225

    Abstract: A semiconductor device contains a Zener-triggered transistor having a Zener diode vertically integrated in a first current node of the Zener-triggered transistor. The first current node includes an n-type semiconductor material contacting a p-type semiconductor material in a substrate. The Zener diode includes an n-type cathode contacting the first current node, and a p-type anode contacting the n-type cathode and contacting the p-type semiconductor material. The semiconductor device may be formed using an implant mask, with an opening for the Zener diode. Boron and arsenic are implanted into the substrate in an area exposed by the opening in the implant mask. The substrate is subsequently heated to diffuse and activate the implanted boron and arsenic. The Zener-triggered transistor may be used in an ESD circuit or a snubber circuit.

    Integrated circuit, LDMOS with trapezoid JFET, bottom gate and ballast drift and fabrication method
    6.
    发明授权
    Integrated circuit, LDMOS with trapezoid JFET, bottom gate and ballast drift and fabrication method 有权

    公开(公告)号：US10529804B2

    公开(公告)日：2020-01-07

    申请号：US15682128

    申请日：2017-08-21

    Applicant: Texas Instruments Incorporated

    Inventor： Jun Cai

    IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78

    Abstract: Disclosed examples include LDMOS transistors and integrated circuits with a gate, a body region implanted in the substrate to provide a channel region under a portion of the gate, a source adjacent the channel region, a drain laterally spaced from a first side of the gate, a drift region including a first highly doped drift region portion, a low doped gap drift region above the first highly doped drift region portion, and a second highly doped region portion above the gap drift region, and an isolation structure extending through the second highly doped region portion into the gap drift region portion, with a first end proximate the drain region and a second end under the gate dielectric layer, where the body region includes a tapered side laterally spaced from the second end of the isolation structure to define a trapezoidal JFET region.

    INTEGRATED CIRCUIT, LDMOS WITH TRAPEZOID JFET, BOTTOM GATE AND BALLAST DRIFT AND FABRICATION METHOD
    7.
    发明申请
    INTEGRATED CIRCUIT, LDMOS WITH TRAPEZOID JFET, BOTTOM GATE AND BALLAST DRIFT AND FABRICATION METHOD 审中-公开

    公开(公告)号：US20190058039A1

    公开(公告)日：2019-02-21

    申请号：US15682128

    申请日：2017-08-21

    Applicant: Texas Instruments Incorporated

    Inventor： Jun Cai

    IPC: H01L29/08 ,  H01L29/66

    Abstract: Disclosed examples include LDMOS transistors and integrated circuits with a gate, a body region implanted in the substrate to provide a channel region under a portion of the gate, a source adjacent the channel region, a drain laterally spaced from a first side of the gate, a drift region including a first highly doped drift region portion, a low doped gap drift region above the first highly doped drift region portion, and a second highly doped region portion above the gap drift region, and an isolation structure extending through the second highly doped region portion into the gap drift region portion, with a first end proximate the drain region and a second end under the gate dielectric layer, where the body region includes a tapered side laterally spaced from the second end of the isolation structure to define a trapezoidal JFET region.

    Methods and Apparatus for LDMOS Devices with Cascaded Resurf Implants and Double Buffers
    9.
    发明申请
    Methods and Apparatus for LDMOS Devices with Cascaded Resurf Implants and Double Buffers 有权
    具有级联植入物和双缓冲液的LDMOS器件的方法和装置

    公开(公告)号：US20160043217A1

    公开(公告)日：2016-02-11

    申请号：US14808991

    申请日：2015-07-24

    Applicant: Texas Instruments Incorporated

    Inventor： Jun Cai

    IPC: H01L29/78 ,  H01L29/10 ,  H01L27/088 ,  H01L21/265 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

    CPC classification number: H01L29/7823 ,  H01L21/26513 ,  H01L21/761 ,  H01L21/76224 ,  H01L21/823814 ,  H01L27/0922 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/1041 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/78 ,  H01L29/7816 ,  H01L29/7835

    Abstract: LDMOS devices are disclosed. An LDMOS device includes at least one drift region disposed in a portion of a semiconductor substrate; at least one isolation structure at a surface of the semiconductor substrate; a D-well region positioned adjacent a portion of the at least one drift region, and an intersection of the drift region and the D-well region forming a junction between first and second conductivity types; a gate structure disposed over the semiconductor substrate; a source contact region disposed on the surface of the D-well region; a drain contact region disposed adjacent the isolation structure; and a double buffer region comprising a first buried layer lying beneath the D-well region and the drift region and doped to the second conductivity type and a second high voltage deep diffusion layer lying beneath the first buried layer and doped to the first conductivity type. Methods are disclosed.

    Abstract translation: 公开了LDMOS器件。 LDMOS器件包括设置在半导体衬底的一部分中的至少一个漂移区域; 在所述半导体衬底的表面处的至少一个隔离结构; 位于所述至少一个漂移区域的一部分附近的D阱区域，以及形成所述第一和第二导电类型之间的接合点的所述漂移区域和所述D阱区域的交点; 设置在半导体衬底上的栅极结构; 源极接触区域，设置在D阱区域的表面上; 设置在所述隔离结构附近的漏极接触区域; 以及双缓冲区域，包括位于D阱区域下方的第一掩埋层和掺杂到第二导电类型的漂移区域，以及位于第一掩埋层下面并掺杂到第一导电类型的第二高电压深度扩散层。 公开了方法。

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