METHODS AND APPARATUS FOR REAL-TIME TRIP SEQUENCE DETECTION FOR CASCADED TRIP EVENTS

    公开(公告)号:US20240362146A1

    公开(公告)日:2024-10-31

    申请号:US18217169

    申请日:2023-06-30

    CPC classification number: G06F11/348 G06F11/3476 G06F2201/88

    Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed for real-time trip sequence detection for cascaded trip events. An example integrated circuit device includes trip detector circuitry, a first counter, a first memory, a second counter, a second memory, and control circuitry in communication with the trip detector circuitry, the control circuitry to, in response to a first trigger detected by the fault detector circuit, store a value of the first counter in the first memory, and in response to a second trigger detected by the fault detector circuit, store a value of the second counter in the second memory. The trip detector circuitry will continue the same detection, identification and counter storage logic for the subsequent triggers limited only by the available storage capacity.

    Methods and apparatus to compensate for power factor loss using a phasor cancellation based compensation scheme

    公开(公告)号:US12051969B2

    公开(公告)日:2024-07-30

    申请号:US18302848

    申请日:2023-04-19

    Inventor: Manish Bhardwaj

    CPC classification number: H02M1/4208 H02M1/4233 H02M7/217

    Abstract: Example power factor correction circuits to correct the power factor of power converters are disclosed. An example power factor correction controller circuit includes a phase locked loop phase angle determiner to determine a first phase angle of an input voltage of the power converter and further includes a compensating current determiner to determine, based on the phase angle, a compensating current to compensate for a capacitive current introduced by at least one filter capacitor of the power converter. The power factor correction controller circuit further includes a switch controller to cause a controlled current drawn by a power stage of the power converter to be adjusted by the compensating current to reduce a phase offset between the first phase angle of the input voltage and a second phase angle of the input current drawn at an input of the power converter.

    Synchronization between devices for PWM waveforms

    公开(公告)号:US11689350B2

    公开(公告)日:2023-06-27

    申请号:US17833971

    申请日:2022-06-07

    CPC classification number: H04L7/0016 H04L7/06

    Abstract: A system includes a first controller configured to transmit a synchronization signal to a second controller. The second controller is configured to produce a PWM signal. The system also includes a counter configured to provide a count for the second controller, where the second controller is configured to initiate rising edges and falling edges of the PWM signal based on the count from the counter. The second controller is also configured to measure an error between a time when the synchronization signal is received at the second controller and an expected time of receipt for the synchronization signal. The second controller is also configured to adjust a period of the counter based at least in part on the error.

    POWERTRAIN ARCHITECTURE FOR A VEHICLE UTILIZING AN ON-BOARD CHARGER

    公开(公告)号:US20220332204A1

    公开(公告)日:2022-10-20

    申请号:US17853292

    申请日:2022-06-29

    Abstract: Techniques related to powertrain architectures for vehicles (such as hybrid electric vehicle/electric vehicles) utilizing an on-board charger are disclosed. The techniques include a device for power regulation, the device comprising a direct current (DC)-to-DC voltage converter configurable to convert a first DC voltage from an alternating current (AC)-to-DC converter to generate a first converted DC voltage to charge a battery, and convert a second DC voltage from the battery to a second converted DC voltage for a DC-to-AC inverter. The inverter couples to a motor. A control circuit is configured to direct an operating mode of the voltage converter.

    METHODS AND APPARATUS TO COMPENSATE FOR POWER FACTOR LOSS USING A PHASOR CANCELLATION BASED COMPENSATION SCHEME

    公开(公告)号:US20230261566A1

    公开(公告)日:2023-08-17

    申请号:US18302848

    申请日:2023-04-19

    Inventor: Manish Bhardwaj

    CPC classification number: H02M1/4208 H02M1/4233 H02M7/217

    Abstract: Example power factor correction circuits to correct the power factor of power converters are disclosed. An example power factor correction controller circuit includes a phase locked loop phase angle determiner to determine a first phase angle of an input voltage of the power converter and further includes a compensating current determiner to determine, based on the phase angle, a compensating current to compensate for a capacitive current introduced by at least one filter capacitor of the power converter. The power factor correction controller circuit further includes a switch controller to cause a controlled current drawn by a power stage of the power converter to be adjusted by the compensating current to reduce a phase offset between the first phase angle of the input voltage and a second phase angle of the input current drawn at an input of the power converter.

    Methods and apparatus to compensate for power factor loss using a phasor cancellation based compensation scheme

    公开(公告)号:US11050344B2

    公开(公告)日:2021-06-29

    申请号:US17029317

    申请日:2020-09-23

    Inventor: Manish Bhardwaj

    Abstract: Example power factor correction circuits to correct the power factor of power converters are disclosed. An example power factor correction controller circuit includes a phase locked loop phase angle determiner to determine a first phase angle of an input voltage of the power converter and further includes a compensating current determiner to determine, based on the phase angle, a compensating current to compensate for a capacitive current introduced by at least one filter capacitor of the power converter. The power factor correction controller circuit further includes a switch controller to cause a controlled current drawn by a power stage of the power converter to be adjusted by the compensating current to reduce a phase offset between the first phase angle of the input voltage and a second phase angle of the an input current drawn at an input of the power converter.

    Powertrain architecture for a vehicle utilizing an on-board charger

    公开(公告)号:US12187146B2

    公开(公告)日:2025-01-07

    申请号:US17853292

    申请日:2022-06-29

    Abstract: Techniques related to powertrain architectures for vehicles (such as hybrid electric vehicle/electric vehicles) utilizing an on-board charger are disclosed. The techniques include a device for power regulation, the device comprising a direct current (DC)-to-DC voltage converter configurable to convert a first DC voltage from an alternating current (AC)-to-DC converter to generate a first converted DC voltage to charge a battery, and convert a second DC voltage from the battery to a second converted DC voltage for a DC-to-AC inverter. The inverter couples to a motor. A control circuit is configured to direct an operating mode of the voltage converter.

    Methods and apparatus to compensate for power factor loss using a phasor cancellation based compensation scheme

    公开(公告)号:US11658564B2

    公开(公告)日:2023-05-23

    申请号:US17326553

    申请日:2021-05-21

    Inventor: Manish Bhardwaj

    CPC classification number: H02M1/4208 H02M1/4233 H02M7/217

    Abstract: Example power factor correction circuits to correct the power factor of power converters are disclosed. An example power factor correction controller circuit includes a phase locked loop phase angle determiner to determine a first phase angle of an input voltage of the power converter and further includes a compensating current determiner to determine, based on the phase angle, a compensating current to compensate for a capacitive current introduced by at least one filter capacitor of the power converter. The power factor correction controller circuit further includes a switch controller to cause a controlled current drawn by a power stage of the power converter to be adjusted by the compensating current to reduce a phase offset between the first phase angle of the input voltage and a second phase angle of the an input current drawn at an input of the power converter.

    Synchronization between devices for PWM waveforms

    公开(公告)号:US11356238B1

    公开(公告)日:2022-06-07

    申请号:US17328561

    申请日:2021-05-24

    Abstract: A system includes a first controller configured to transmit a synchronization signal to a second controller. The second controller is configured to produce a PWM signal. The system also includes a counter configured to provide a count for the second controller, where the second controller is configured to initiate rising edges and falling edges of the PWM signal based on the count from the counter. The second controller is also configured to measure an error between a time when the synchronization signal is received at the second controller and an expected time of receipt for the synchronization signal. The second controller is also configured to adjust a period of the counter based at least in part on the error.

    TRANSIENT CONTROL FOR POWER FACTOR CORRECTION

    公开(公告)号:US20200313548A1

    公开(公告)日:2020-10-01

    申请号:US16846494

    申请日:2020-04-13

    Abstract: A drive circuit includes a transient detector that includes a detector input to receive a loop error signal from a phased locked loop (PLL) and generates a transient detected output signal if a transient is detected in an alternating current (AC) input voltage. A controller includes a controller input to receive the transient detected output signal from the transient detector and a feedback input to sense the AC input voltage provided to a bridge circuit. The controller is configured to apply a PLL angle output signal from the PLL to control switch output signals to the bridge circuit if the transient detected output signal is not generated and configured to apply the AC input voltage sensed from the feedback input to control the switch output signals to the bridge circuit if the transient detected output signal is generated.

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