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公开(公告)号：US09717426B2
公开(公告)日：2017-08-01
申请号：US14837179
申请日：2015-08-27
Applicant: Texas Instruments Incorporated
Inventor： Ajit Sharma , Sriram Narayanan , Srinath Mathur Ramaswamy , Arup Polley , Seung Bae Lee , Wen Li
CPC classification number: A61B5/02427 , A61B5/6826 , A61B5/7228 , A61B2562/0238
Abstract: The circuitry of an optical receiver reduces the ambient DC component and the pleth DC component to leave a pleth signal with substantially only a pleth AC component. The circuitry also provides gain control and can provide transmit power control to change the range of the pleth AC component to occupy a desired input range of an analog-to-digital converter.
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公开(公告)号：US10651803B2
公开(公告)日：2020-05-12
申请号：US15816369
申请日：2017-11-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Seung Bae Lee , Michael Edwin Butenhoff , Sudhir Nagaraj
Abstract: Reducing noise for an amplifier-based system circuit that comprises a first differential input pair and a second differential input pair, a first input stage circuit connected to the first differential input pair, wherein the first input stage is configured with a first transconductance value, a second input stage circuit connected to the second differential input pair, wherein the second input stage is configured with a second transconductance value that is less than the first transconductance value, a transimpedance circuit coupled to the first input stage circuit and the second input stage circuit, and a feedback loop circuit coupled to the transimpedance circuit and to the second differential input pair, wherein the feedback loop circuit is not connected to the first differential input pair.
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公开(公告)号：US09667289B2
公开(公告)日：2017-05-30
申请号：US15084052
申请日：2016-03-29
Applicant: Texas Instruments Incorporated
Inventor： Arup Polley , Ajit Sharma , Seung Bae Lee , Sriram Narayanan , Srinath Ramaswamy
CPC classification number: H04B1/1036 , H04B1/0028 , H04B2001/1054
Abstract: Reduced noise and power with rapid settling time and increased performance in multi-modal analog multiplexed data acquisition systems. An example apparatus arrangement includes a circuit input configured to receive a plurality of analog input signals; an analog to digital converter circuit configured to output a digital representation of an analog voltage; a selection circuit configured to select one of the analog input signals received at the circuit input; a buffer coupled to receive the selected one of the analog input signals; a filter coupled to the buffer and configured to perform a high bandwidth sample operation and a low bandwidth sample operation and having a filter output, responsive to a control signal; and a sampling capacitor coupled to the filter to sample the filter output, and having an output coupled to the analog to digital converter. Methods and additional apparatus arrangements are disclosed.
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公开(公告)号：US20160235313A1
公开(公告)日：2016-08-18
申请号：US14837179
申请日：2015-08-27
Applicant: Texas Instruments Incorporated
Inventor： Ajit Sharma , Sriram Narayanan , Srinath Mathur Ramaswamy , Arup Polley , Seung Bae Lee , Wen Li
CPC classification number: A61B5/02427 , A61B5/6826 , A61B5/7228 , A61B2562/0238
Abstract: The circuitry of an optical receiver reduces the ambient DC component and the pleth DC component to leave a pleth signal with substantially only a pleth AC component. The circuitry also provides gain control and can provide transmit power control to change the range of the pleth AC component to occupy a desired input range of an analog-to-digital converter.
Abstract translation: 光接收器的电路减少环境直流分量和百分比直流分量，以便基本上只有一个良好的交流分量留下一个信号。 电路还提供增益控制，并且可以提供发射功率控制，以改变百分之AC组件的范围，以占据模数转换器的期望输入范围。
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5.发明申请Methods and Apparatus for Reducing Noise, Power and Settling Time in Multi-Modal Analog Multiplexed Data Acquisition Systems 有权用于降低多模态模拟多路复用数据采集系统中噪声，功率和稳定时间的方法和装置公开(公告)号：US20160380660A1
公开(公告)日：2016-12-29
申请号：US15084052
申请日：2016-03-29
Applicant: Texas Instruments Incorporated
Inventor： Arup Polley , Ajit Sharma , Seung Bae Lee , Sriram Narayanan , Srinath Ramaswamy
IPC: H04B1/10
CPC classification number: H04B1/1036 , H04B1/0028 , H04B2001/1054
Abstract: Reduced noise and power with rapid settling time and increased performance in multi-modal analog multiplexed data acquisition systems. An example apparatus arrangement includes a circuit input configured to receive a plurality of analog input signals; an analog to digital converter circuit configured to output a digital representation of an analog voltage; a selection circuit configured to select one of the analog input signals received at the circuit input; a buffer coupled to receive the selected one of the analog input signals; a filter coupled to the buffer and configured to perform a high bandwidth sample operation and a low bandwidth sample operation and having a filter output, responsive to a control signal; and a sampling capacitor coupled to the filter to sample the filter output, and having an output coupled to the analog to digital converter. Methods and additional apparatus arrangements are disclosed.
Abstract translation: 在多模式模拟复用数据采集系统中，通过快速建立时间和更高性能降低噪声和功耗。 示例性装置配置包括被配置为接收多个模拟输入信号的电路输入; 模数转换器电路，被配置为输出模拟电压的数字表示; 选择电路，被配置为选择在所述电路输入处接收的所述模拟输入信号之一; 耦合以接收所选择的一个模拟输入信号的缓冲器; 滤波器，耦合到所述缓冲器并且被配置为响应于控制信号执行高带宽采样操作和低带宽采样操作并具有滤波器输出; 以及耦合到所述滤波器以对所述滤波器输出进行采样并且具有耦合到所述模数转换器的输出的采样电容器。 公开了方法和附加装置布置。
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Patent Agency Ranking
公开(公告)号：US11487381B2
公开(公告)日：2022-11-01
申请号：US16512020
申请日：2019-07-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Wei-Yan Shih , Steve Kummerl , Mark Stephen Toth , Alok Lohia , Terry Lee Sculley , Seung Bae Lee , Scott Robert Summerfelt
Abstract: An integrated force sensing element includes a piezoelectric sensor formed in an integrated circuit (IC) chip and a strain gauge at least partially overlying the piezoelectric sensor, where the piezoelectric sensor is able to flex. A human-machine interface using the integrated force sensing element is also disclosed and may include a conditioning circuit, temperature gauge, FRAM and a processor core.
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公开(公告)号：US20190158033A1
公开(公告)日：2019-05-23
申请号：US15816369
申请日：2017-11-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Seung Bae Lee , Michael Edwin Butenhoff , Sudhir Nagaraj
Abstract: Reducing noise for an amplifier-based system circuit that comprises a first differential input pair and a second differential input pair, a first input stage circuit connected to the first differential input pair, wherein the first input stage is configured with a first transconductance value, a second input stage circuit connected to the second differential input pair, wherein the second input stage is configured with a second transconductance value that is less than the first transconductance value, a transimpedance circuit coupled to the first input stage circuit and the second input stage circuit, and a feedback loop circuit coupled to the transimpedance circuit and to the second differential input pair, wherein the feedback loop circuit is not connected to the first differential input pair.
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公开(公告)号：US20170123548A1
公开(公告)日：2017-05-04
申请号：US14926265
申请日：2015-10-29
Applicant: Texas Instruments Incorporated
Inventor： Wei-Yan Shih , Steve Kummerl , Mark Stephen Toth , Alok Lohia , Terry Lee Sculley , Seung Bae Lee , Scott Robert Summerfelt
IPC: G06F3/041
CPC classification number: G06F3/0414 , G06F3/0416
Abstract: An integrated force sensing element includes a piezoelectric sensor formed in an integrated circuit (IC) chip and a strain gauge at least partially overlying the piezoelectric sensor, where the piezoelectric sensor is able to flex. A human-machine interface using the integrated force sensing element is also disclosed and may include a conditioning circuit, temperature gauge, FRAM and a processor core.
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9.发明授权公开(公告)号：US09432044B1
公开(公告)日：2016-08-30
申请号：US14973902
申请日：2015-12-18
Applicant: Texas Instruments Incorporated
Inventor： Seung Bae Lee , Ajit Sharma , Srinath Ramaswamy
CPC classification number: H03M1/1061 , H03M1/468 , H03M1/687
Abstract: A multi-segment capacitive successive approximation analog to digital converter (SAR ADC) is calibrated by determining an error voltage for each of a plurality of most significant bit (MSB) capacitors in a first segment using a calibration DAC. The first segment is connected to the second segment by an attenuation capacitor. Each of the error voltages corresponding to the MSB capacitors is digitized to form a set of digitized error voltages. An error voltage for each of a plurality of less significant bit (LSB) capacitors in at least the second segment is calculated by summing the set of digitized error voltages to form a sum of error voltages (sum(e)) and assigning a percentage of sum(e) as the error voltage for each of the LSB capacitors, such that a mismatch in the attenuation capacitor is mitigated.
Abstract translation: 通过使用校准DAC确定第一段中的多个最高有效位（MSB）电容器中的每一个的误差电压来校准多段电容逐次逼近模数转换器（SAR ADC）。 第一段通过衰减电容器连接到第二段。 对应于MSB电容器的每个误差电压被数字化以形成一组数字化的误差电压。 至少第二段中的多个较低有效位（LSB）电容器中的每一个的误差电压通过将数字化误差电压的集合相加以形成误差电压（sum（e））的和并且分配 总和（e）作为每个LSB电容器的误差电压，使得减小衰减电容器的失配。
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公开(公告)号：US09319059B1
公开(公告)日：2016-04-19
申请号：US14732676
申请日：2015-06-06
Applicant: Texas Instruments Incorporated
Inventor： Ajit Sharma , Seung Bae Lee , Srinath Mathur Ramaswamy , Sriram Narayanan , Arup Polley
CPC classification number: H03M1/46 , H03M1/1057 , H03M1/38 , H03M1/403 , H03M1/468
Abstract: The silicon real estate required for the semiconductor fabrication of a calibrated capacitor-based successive approximation register (SAR) analog-to-digital converter (ADC) (100) is substantially reduced by using a number of shared capacitors (SC1-SCs−1) which are used as calibration capacitors when operating in a calibration mode and as bit capacitors when operating in a normal mode.
Abstract translation: 基于校准电容器的逐次逼近寄存器（SAR）模数转换器（ADC）（100）的半导体制造所需的硅绝缘体通过使用多个共用电容器（SC1-SCs-1）而大大降低， 它们在校准模式下工作时用作校准电容器，在正常模式下工作时用作位电容器。
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