公开(公告)号：EP0367466A3

公开(公告)日：1991-07-24

申请号：EP89310869.6

申请日：1989-10-23

Applicant: THE GENERAL ELECTRIC COMPANY, p.l.c.

Inventor： Haws, Stephen Anthony

IPC: G02F1/1335 ,  G03F7/00

CPC classification number: G02F1/133516 ,  G02F1/133512

Abstract: In a process for depositing a planarising material in spaces (5,6) between a pattern of regions (1,2,3), such as dye stripes or dots, on a substrate (4), the planarising material is deposited as a layer (7) over the pattern. The substrate is irradiated, from the reverse side, by a source (8) of radiation, such as UV, to which the pattern material is opaque and to which the planarising material is responsive such that it is rendered insoluble to a particular solvent. The radiation acts on only those parts (9-12) of the planarising material which are in the spaces. The remainder (13-15) of the planarising layer is then removed by use of the solvent. Alternatively, or additionally, an ITO or other UV transparent layer may be formed over the pattern and a layer of resist formed thereover. The radiation then passes through the spaces and acts on only the resist areas over the spaces to render them soluble. Those areas and the ITO layer beneath them are then removed by etching, leaving ITO areas accurately aligned with the pattern. The process may be used in the manufacture of LC displays or semiconductor devices.

公开(公告)号：EP0367466A2

公开(公告)日：1990-05-09

申请号：EP89310869.6

申请日：1989-10-23

Applicant: THE GENERAL ELECTRIC COMPANY, p.l.c.

Inventor： Haws, Stephen Anthony

IPC: G02F1/1335 ,  G03F7/00

CPC classification number: G02F1/133516 ,  G02F1/133512

Abstract: In a process for depositing a planarising material in spaces (5,6) between a pattern of regions (1,2,3), such as dye stripes or dots, on a substrate (4), the planarising material is deposited as a layer (7) over the pattern. The substrate is irradiated, from the reverse side, by a source (8) of radiation, such as UV, to which the pattern material is opaque and to which the planarising material is responsive such that it is rendered insoluble to a particular solvent. The radiation acts on only those parts (9-12) of the planarising material which are in the spaces. The remainder (13-15) of the planarising layer is then removed by use of the solvent. Alternatively, or additionally, an ITO or other UV transparent layer may be formed over the pattern and a layer of resist formed thereover. The radiation then passes through the spaces and acts on only the resist areas over the spaces to render them soluble. Those areas and the ITO layer beneath them are then removed by etching, leaving ITO areas accurately aligned with the pattern. The process may be used in the manufacture of LC displays or semiconductor devices.

Abstract translation: 在用于在基板（4）上的区域（1,2,3）（例如染色条纹或点）图案之间的空间（5,6）中沉积平纹材料的过程中，平面化材料被沉积为层 （7）在图案上。 衬底从反面通过诸如UV的辐射源（8）照射，图案材料不透明的区域，并且平面化材料对其起反应性，从而使其不溶于特定的溶剂。 辐射仅作用于空间中平面化材料的那些部分（9-12）。 然后通过使用溶剂除去平坦化层的剩余部分（13-15）。 或者或另外，可以在图案上方形成ITO或其它UV透明层，并在其上形成抗蚀剂层。 然后，辐射通过空间，仅作用在空间上的抗蚀剂区域上，使其变得可溶。 然后通过蚀刻去除那些区域和其下面的ITO层，留下ITO区域与图案精确对准。 该方法可用于LC显示器或半导体器件的制造。

公开(公告)号：EP0430487B1

公开(公告)日：1995-05-17

申请号：EP90312404.8

申请日：1990-11-14

Applicant: THE GENERAL ELECTRIC COMPANY, p.l.c.

Inventor： Tomes, Derek William ,  Lowe, Antony John ,  Rundle, Patrick Colin ,  Haws, Stephen Anthony

IPC: G02F1/136

CPC classification number: G02F1/1368 ,  G02F2001/136268 ,  G02F2201/122 ,  G02F2202/104

公开(公告)号：EP0430487A3

公开(公告)日：1992-04-29

申请号：EP90312404.8

申请日：1990-11-14

Applicant: THE GENERAL ELECTRIC COMPANY, p.l.c.

Inventor： Tomes, Derek William ,  Lowe, Antony John ,  Rundle, Patrick Colin ,  Haws, Stephen Anthony

IPC: G02F1/136

CPC classification number: G02F1/1368 ,  G02F2001/136268 ,  G02F2201/122 ,  G02F2202/104

Abstract: In a method of forming a matrix addressable display comprising a group of switchable cells (C11,C12,C21, C22), such as liquid crystal cells, having electrodes (3,5) on each of two parallel plates and thin-film drive transistors (T11,T12,T21,T22) disposed on one of the plates, gate resistors (33,35) are provided by elongate doped polysilicon regions (49) connecting the gate electrodes to address lines (23,25). The gate resistors prevent short-circuiting of the address lines in the event of a gate short-circuit occurring in any of the transistors.

公开(公告)号：EP0430487A2

公开(公告)日：1991-06-05

申请号：EP90312404.8

申请日：1990-11-14

Applicant: THE GENERAL ELECTRIC COMPANY, p.l.c.

Inventor： Tomes, Derek William ,  Lowe, Antony John ,  Rundle, Patrick Colin ,  Haws, Stephen Anthony

IPC: G02F1/136

CPC classification number: G02F1/1368 ,  G02F2001/136268 ,  G02F2201/122 ,  G02F2202/104

Abstract: In a method of forming a matrix addressable display comprising a group of switchable cells (C11,C12,C21, C22), such as liquid crystal cells, having electrodes (3,5) on each of two parallel plates and thin-film drive transistors (T11,T12,T21,T22) disposed on one of the plates, gate resistors (33,35) are provided by elongate doped polysilicon regions (49) connecting the gate electrodes to address lines (23,25). The gate resistors prevent short-circuiting of the address lines in the event of a gate short-circuit occurring in any of the transistors.

Abstract translation: 在形成矩阵可寻址显示器的方法中，包括一组可切换单元（C11，C12，C21，C22），诸如液晶单元，在两个平行板中的每一个上具有电极（3,5）和薄膜驱动晶体管 （T11，T12，T21，T22），栅极电阻器（33,35）由将栅电极连接到地址线（23,25）的细长掺杂多晶硅区域（49）提供。 栅极电阻器防止在任何晶体管中发生栅极短路的情况下地址线短路。