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公开(公告)号：DE60223657D1
公开(公告)日：2008-01-03
申请号：DE60223657
申请日：2002-02-25
Applicant: TOA CORP
Inventor： EJIMA KEN ICHI
Abstract: A master clock signal source (10) generates a master clock signal having a frequency equal to N times the bit rate of received data, where N is a positive integer. A modulo-N counter (12) counts the master clock signal. An edge detecting circuit (4) detects a transition of the received data from a H level to a L level. A counter (8) counts the master clock signal and resets the modulo-N counter (12) if the count counted during a time period in which three edge representative signals occur is 2N. In accordance with the count in the modulo-N counter 12, a clock generating unit 14 generates a clock signal.
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公开(公告)号：EP1367762A4
公开(公告)日：2006-05-17
申请号：EP02700759
申请日：2002-02-25
Applicant: TOA CORP
Inventor： EJIMA KEN ICHI
CPC classification number: H04L7/0331
Abstract: A master clock signal source (10) generates a master clock signal of a frequency which is N (N is a positive integer) times the bit rate of the received data. An N-ary counter (12) counts the master clock signals. An edge detector circuit (4) detects the transition from an H level to an L level of the received data. A counter (8) counts the master clock signals. When the count becomes 2N while three edge detection signals are generated, the counter (8) resets the N-ary counter (12). A clock generating unit (14) generates a clock signal according to the count made by the N-ary counter (12).
Abstract translation: 主时钟信号源（10）产生具有等于接收数据的比特率的N倍的频率的主时钟信号，其中N是正整数。 模N计数器（12）对主时钟信号进行计数。 边缘检测电路（4）检测接收数据从H电平到L电平的转变。 如果在发生三个边缘代表信号的时间段内计数的计数器为2N，则计数器（8）对主时钟信号进行计数并复位模N计数器（12）。 根据模N计数器12中的计数，时钟产生单元14产生时钟信号。
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公开(公告)号：DE60223657T2
公开(公告)日：2008-04-10
申请号：DE60223657
申请日：2002-02-25
Applicant: TOA CORP
Inventor： EJIMA KEN ICHI
Abstract: A master clock signal source (10) generates a master clock signal having a frequency equal to N times the bit rate of received data, where N is a positive integer. A modulo-N counter (12) counts the master clock signal. An edge detecting circuit (4) detects a transition of the received data from a H level to a L level. A counter (8) counts the master clock signal and resets the modulo-N counter (12) if the count counted during a time period in which three edge representative signals occur is 2N. In accordance with the count in the modulo-N counter 12, a clock generating unit 14 generates a clock signal.
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