公开(公告)号：JP2002151909A

公开(公告)日：2002-05-24

申请号：JP2001228193

申请日：2001-07-27

Applicant: TOSHIBA CORP

Inventor： FUKUYA HIROYUKI ,  KAYANO HIROYUKI ,  TERAJIMA YOSHIAKI ,  AIGA FUMIHIKO ,  YAMAZAKI MUTSUKI ,  KATO RIICHI

IPC: H01P1/203 ,  H01P1/213 ,  H04B1/50

Abstract: PROBLEM TO BE SOLVED: To provide superconducting filters adopting a flat transmission line structure that has a sufficient S/N without causing no interference even when they are placed close to each other and that has an excellent cooling efficiency without sacrificing the compactness that is a feature of the flat transmission line structure. SOLUTION: The wireless transmitter-receiver is provided with a superconducting reception filter (2) adopting the flat transmission line structure that selects signals received from an antenna and with a superconducting transmission filter (1) adopting the planar transmission line structure that selects signals to be sent to the antenna, which are contained in a heat insulation package spaced at an interval of nearly a wavelength of a transmission signal. The components, resonance elements (22) and signal input output lines (21, 23) of the reception filter (2) and the components, resonance elements (12) and signal input output lines (11, 13) of the transmission filter (1) are placed not in parallel with each other.

公开(公告)号：JPH10256403A

公开(公告)日：1998-09-25

申请号：JP6130497

申请日：1997-03-14

Applicant: TOSHIBA CORP

Inventor： OBA RYUJI ,  KATO RIICHI ,  TANAMOTO TETSUSHI ,  SUGIYAMA NAOHARU

IPC: H01L21/8247 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To make it possible to make an island very fine, in the order of nanometers, by forming a recess between a pair of electrodes and then forming two tunnel junctions so that they may be brought into contact with side faces of the recess and placing, in the tunnel junctions, conductive fine particles which can hold one electron. SOLUTION: For example, an oxide film 12 and an n polysilicon layer are formed on a P type silicon substrate 11 and then a pattern of an electrode 13 is formed and then, with the electrode pattern used as a mask, an n layer 14 is formed and, after that, the oxide film is etched. By this method, the oxide film 12 is cut from outside and thereby a fine recess 15 is formed between the electrodes 13 and 14. Nextly, silicon fine particles are scattered on the substrate to form, in the fine recess 15, a double tunnel junction wherein fine silicon particles which will become islands exist. In this case, only such silicon fine particles that are smaller than the width of the recess can enter the fine recess 15 and therefore islands can be made very fine, in the order of nanometers. As a result, by controlling the thickness of the oxide film 12, basic elements of the double tunnel junction including the particle diameter of the islands and a capacity can be well controlled.

公开(公告)号：JPH09260632A

公开(公告)日：1997-10-03

申请号：JP6155996

申请日：1996-03-19

Applicant: TOSHIBA CORP

Inventor： TANAMOTO TETSUSHI ,  KATO RIICHI

IPC: H01L29/06 ,  H01L29/66

Abstract: PROBLEM TO BE SOLVED: To prevent generation of a leak current and ensure a necessary current by a method, wherein there is provided an output carrier control part comprising a conductive region where energy is quantized and a barrier region where an energy barrier is higher for a carrier than for a plurality of conductive regions. SOLUTION: A polycrystalline silicon film 4 selectively remains behind in a side wall of a monocrystal silicon film 2 by entire face etching. This remaining polycrystalline silicon film 4 functions as a multi-tunneling junction layer for reducing a leak current. In this case, a grain in the polycrystalline silicon film 4 functions as a quantum dot of the multi-tunneling junction layer. As a result, only electrons corresponding to an energy level quantized in the multi-tunneling junction layer can reach a tunnel barrier layer. Accordingly, as tunneling of a carrier can be suppressed, it becomes possible to prevent effectively the leak current from flowing in an island.

公开(公告)号：JPH0435037A

公开(公告)日：1992-02-05

申请号：JP14255090

申请日：1990-05-31

Applicant: TOSHIBA CORP

Inventor： ENDO NAOHIKO ,  KATO RIICHI

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/737

Abstract: PURPOSE:To provide a high-speed transistor by forming an emitter region composed of two layers with different doping concentrations, and a base region composed of two layers with different band gaps. CONSTITUTION:An emitter region includes a first emitter layer 1 and a second emitter layer 6 that is composed of the same material but has a lower doping concentration than the first emitter layer. A base region includes a first base layer 5, which consists of the same material as the emitter region and becomes a perfect depletion layer at thermal equilibrium, and a second base layer 4 having a smaller band gap than the first base layer. According to this structure, holes can hardly enter the first base layer 5 and the second emitter layer 6 from the second base layer 4. This reduces recombination current and decreases the number of holes that return to the first emitter layer 7; therefore, conductivity modulation can be suppressed. In addition, the critical film thickness of the whole base region is relaxed, so that the effective base thickness can be increased to an extent corresponding to the thickness of the second base layer to reduce the sheet resistance of the base.

公开(公告)号：JPH03280433A

公开(公告)日：1991-12-11

申请号：JP23136590

申请日：1990-08-31

Applicant: TOSHIBA CORP

Inventor： KATO RIICHI ,  ENDO NAOHIKO

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/737

Abstract: PURPOSE:To enable the smooth conductive band shape, forming no potential barrier against electrons near a base-collector junction of a conductive band, to be taken by a method wherein the first hetero junction bipolar transistor divides a base layer and a collector layer respectively into multiple layers while in the base layer, a layer in lower impurity concentration than that in an emitter layer side is provided on a collector layer side. CONSTITUTION:A double hetero-structure made of a material comprising an emitter layer and a collector layer in larger band gap than that of a base layer is erected. The base layer and the collector layer are divided into two layers. Assuming the impurity doping concentration of the layer 6 in the base layer on the side near the emitter layer 4 to be N2 and the thickness to be W2 likewise, the impurity doping concentration of the layer 5 on the side near the collector layer 11 to be N3 and the thickness to be W3 as well as the impurity doping concentration of the layer 4 in the collector layer on the side near the base layer to be N4 while the impurity doping concentration of the layer 3 on the side near the sub-collector layer 11 to be N5, following relation i.e., W2>=W3, N2>=N3, N4>=N5 or N2>=N3, N4>=N5 shall be satisfied.

公开(公告)号：JPH01264261A

公开(公告)日：1989-10-20

申请号：JP9158388

申请日：1988-04-15

Applicant: TOSHIBA CORP

Inventor： KATO RIICHI

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/205 ,  H01L29/72 ,  H01L29/737

Abstract: PURPOSE:To shorten the collector transit time without increasing the base transit time by forming a sixth semiconductor layer, of a second conductivity type, whose impurity concentration is lower than that of a second semiconductor layer and which is used as a collector region. CONSTITUTION:The following are epitaxially grown one after another on a substrate 1: an n type GaAs layer 2 whose impurity concentration is 2X10 cm ; p type GaAs 3 whose impurity concentration is 1X10 cm ; an undoped GaAs layer 4; a p type GaAs layer 5 whose impurity concentration is 1X10 cm ; a p type GaAs layer 6 whose impurity concentration is 1X10 -cm ; an n-type AlGaAs layer 7 whose impurity concentration is 3mu10 cm and whose thickness is 500Angstrom ; an n type GaAs layer 8 whose impurity concentration is 2X10 cm . Then, an insulating layer 121, for device isolation use, which reaches the substrate 1 and an insulating layer 122 used to separate electrodes are first formed, an etching operation reaching the p type GaAs layer 6 is executed; after that, a CVD SiO2 film 13 is formed; after that, a CVD SiO2 film 13 is formed on a whole face. Then, an etching operation reaching the n type GaAs layer 2 is executed, a collector electrode 11, an emitter electrode 9 and a base electrode 10 are formed.

公开(公告)号：JPS6153769A

公开(公告)日：1986-03-17

申请号：JP17413384

申请日：1984-08-23

Applicant: Toshiba Corp

Inventor： KATO RIICHI

IPC: H01L29/205 ,  H01L21/331 ,  H01L29/73 ,  H01L29/737

CPC classification number: H01L29/7371

Abstract: PURPOSE:To operate the transistor rapidly, by forming two-dimentional electrons between a first conductor layer containing no impurity and a second conductive layer having a wider band gap than that of the first conductive layer and containing an n type impurity, for conducting electricity to an emitter or a collector. CONSTITUTION:An undoped GaAs layer 11a, n -AlGaAs layer 12, n-AlGaAs layer 13, p -GaAs layer 14, n-GaAs layer 15 and an n -GaAs layer 16 are grown by the MBE process or the like on a semi-insulating substrate 11, successively in that order. The layers are formed in stepped form by the etching or the like, acording to the element pattern. An p outer base layer 17 or an n collector layer 18 is formed by the ion implantation or the like, and electrodes are formed. Thus, the structure with the collector at the top is provided, and therefore the bulk emitter resistance is substantially reduced by two-dimentional electron gas.

Abstract translation: 目的：为了快速地操作晶体管，通过在不含杂质的第一导体层和具有比第一导电层宽的带隙的第二导电层之间形成二维电子并且包含n型杂质，用于将电 发射器或收集器。 构成：未掺杂的GaAs层11a，n + AlGaAs层12，n-AlGaAs层13，p + GaAs层14，n-GaAs层15和n + GaAs层16通过 半绝缘基板11上的MBE工艺等，依次依次进行。 这些层通过蚀刻等以阶梯状形成，与元件图案一致。 通过离子注入等形成p + +基底层17或n +集电极层18，形成电极。 因此，提供了在顶部具有集电极的结构，因此通过二维电子气体显着减少体发射极电阻。

公开(公告)号：JPS6153768A

公开(公告)日：1986-03-17

申请号：JP17413284

申请日：1984-08-23

Applicant: Toshiba Corp

Inventor： KATO RIICHI ,  KURATA MAMORU

IPC: H01L29/205 ,  H01L21/331 ,  H01L29/20 ,  H01L29/73 ,  H01L29/737

CPC classification number: H01L29/7371

Abstract: PURPOSE:To realize high-speed switching, by decreasing the concentration of impurity in a collector layer in a stepped manner or continuously from a base layer. CONSTITUTION:An N type layer 12a of GaAs with an N type dopand such as Si is formed on a semi-insulating Si sbustrate 11. An N type layer 12b of GaAs having a concentration n1 is formed thereon, and an N type layer 12c of GaAs having a concentration n2 is formed thereon. Further a P type layer 13a of GaAs with a P type dopand such as Be, an N type layer 14a of AlGaAs and an N type layer 14b of AlGaAs are formed successively in that order. Ions of P type dopand such as Be are implanted to form an outer base region 13a. The concentration n1 is determined in accordance with the thickness d of the N type layer of the outer base after the ion implantation which is previously calculated. On the other hand, the concentration n2 is determined in accordance with the density of current flowing during operation of the transistor, such that the concentration of electrons in the collector depletion layer is equal to or lower than that of the impurity.

Abstract translation: 目的：通过逐步降低集电体层中的杂质浓度或从基底层连续地降低杂质浓度，实现高速切换。 构成：在半绝缘Si基底11上形成有N型掺杂剂如GaAs的N + N型层12a，在其上形成具有浓度为n1的GaAs的N型层12b，N型 在其上形成具有浓度n2的GaAs层12c。 此外，依次形成具有P型掺杂剂的诸如Be，AlGaAs的N型层14a和AlGaAs的N +型层14b的P +型层13a。 植入诸如Be的P型掺杂物的离子以形成外部基极区域13a。 浓度n1根据预先计算的离子注入后的外基层的N型层的厚度d来确定。 另一方面，浓度n2根据在晶体管工作期间流动的电流的密度来确定，使得集电极耗尽层中的电子浓度等于或低于杂质浓度。

公开(公告)号：JPH076147A

公开(公告)日：1995-01-10

申请号：JP14897793

申请日：1993-06-21

Applicant: TOSHIBA CORP

Inventor： KURATA MAMORU ,  KATO RIICHI ,  NAKAMURA SHIN

IPC: G05B13/02 ,  G06F15/18 ,  G06G7/60 ,  G06N99/00

Abstract: PURPOSE:To provide an arithmetic unit applying a neural network capable of quickly applying correct answers to all input values by a sufficiently long bit length. CONSTITUTION:In this neural network arithmetic unit having plural computing elements D1 to D10 connected to the post stages of input means for converting external input signals at the rate of one to one, mutually connecting all the elements D1 to D10 and constituting respective elements so that a feedback signal obtained by multiplying a signal outputted from one element by a prescribed connection coefficient is added to another feedback signal to another element and an output signal from an input means is applied to the other element and signals from all the elements when the unit arrives at a balanced state or a prescribed time has elapsed are outputted as output signals corresponding to the external input signal, the elements D1 to D10 are self-saturatedly coupled, coupling coefficients other than that of self saturated coupling and the contents of conversion are determined based upon I/O relation to be applied to the arithmetic unit and a connection coefficient relating to the self saturatied coupling is set to a prescribed value to control I/O characteristics including the degree of approximation in the I/O relation of the unit and its operating speed.

公开(公告)号：JPH03241867A

公开(公告)日：1991-10-29

申请号：JP3905490

申请日：1990-02-20

Applicant: TOSHIBA CORP

Inventor： ENDO NAOHIKO ,  KATO RIICHI

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737

Abstract: PURPOSE:To obtain an HBT excellent in breakdown strength and high speed operation by a method wherein a base region is composed of a low concentration first base layer which is possessed of the same band gap with an emitter region and turns into a perfect depletion layer in a thermal equilibrium state and a high concentration second base layer patterned in grating. CONSTITUTION:An N -type Si layer 2 serving as a collector contact layer is epitaxially grown in succession on a P -type Si substrate 1, and an N-type Si layer 3 serving as a collector layer is formed thereon. A P -Si1-XGeX (0.2 cm -1X10 cm in impurity concentration and 300-800Angstrom in thickness, is formed thereon as a second base layer 4, and a P -type Si layer, 8X10 cm -1X10 cm in impurity concentration and 100-500Angstrom in thickness, is laminated thereon as a first base layer 5 to constitute a base region. furthermore, an N-type Si emitter layer 6 and an N -type Si emitter cap layer 7 are formed to constitute an HBT.