公开(公告)号：EP2078979A1

公开(公告)日：2009-07-15

申请号：EP08156725.7

申请日：2008-05-22

Applicant: TPO Displays Corp.

Inventor： Collins, Paul

IPC: G02F1/1362

CPC classification number: G02F1/136213 ,  G02F1/13454 ,  G02F2001/13606 ,  G02F2001/136218 ,  G02F2202/104 ,  G09G2320/0219

Abstract: A display pixel arrangement is provided in which the row electrode metal layer (58), defining the scan lines and the storage capacitance lines, is arranged between the pixel electrode layer (64) and the metal layer (50) defining the columns (50a). In this way, a portion of the storage capacitance line extending above and along the column (data)line can be used to provide a shield between the pixel electrodes (64) and the column lines (50a), thereby reducing capacitive coupling between adjacent pixels, even if the pixel electrodes overlap the column lines. This improves the performance of digital to analogue conversion, particularly if charge sharing between columns is used.

Abstract translation: 提供了一种显示像素布置，其中限定扫描线和存储电容线的行电极金属层（58）布置在限定列（50a）的像素电极层（64）和金属层（50）之间， 。 以这种方式，可以使用在列（数据）线上方和沿着列（数据）线延伸的一部分存储电容线来在像素电极（64）和列线（50a）之间提供屏蔽，从而减少相邻像素之间的电容耦合 即使像素电极与列线重叠。 这提高了数字到模拟转换的性能，特别是如果使用列之间的电荷共享。