公开(公告)号：EP1798734A2

公开(公告)日：2007-06-20

申请号：EP06124962.9

申请日：2006-11-28

Applicant: TPO Displays Corp.

Inventor： Lee, Ching-Hone

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G3/3674 ,  G09G3/3685 ,  G09G2310/0286 ,  G09G2330/021

Abstract: Systems for displaying images are provided. A representative system comprises a signal driving circuit comprising a plurality of shift (SR1...SRN) registers connected in series and controlled only by a first clock (CLK1) and a second clock (CLK2), generating corresponding driving pulses in turn in response to a start pulse (STP). Each shift register comprises a pulse generation unit with a first clock input terminal receiving one of the first (AT) and the second clocks (BT) and a first power terminal (P1) coupled to a first power voltage (VDD), and a leakage protection unit coupled to the pulse generation unit, electrically separating the first power voltage from the received clock at the first clock input terminal.

Abstract translation: 提供显示图像的系统。 代表性系统包括信号驱动电路，该信号驱动电路包括串联连接并仅由第一时钟（CLK1）和第二时钟（CLK2）控制的多个移位寄存器（SR1 ... SRN），依次响应于相应的驱动脉冲 到起始脉冲（STP）。 每个移位寄存器包括具有接收第一（AT）和第二时钟（BT）中的一个的第一时钟输入端和与第一电源电压（VDD）耦合的第一电源端（P1）的脉冲产生单元，以及泄漏 保护单元，耦合到所述脉冲发生单元，在所述第一时钟输入端子处将所述第一电源电压与所接收的时钟电分离。

公开(公告)号：EP1798734A3

公开(公告)日：2009-03-04

申请号：EP06124962.9

申请日：2006-11-28

Applicant: TPO Displays Corp.

Inventor： Lee, Ching-Hone

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G3/3674 ,  G09G3/3685 ,  G09G2310/0286 ,  G09G2330/021

Abstract: Systems for displaying images are provided. A representative system comprises a signal driving circuit comprising a plurality of shift (SR1...SRN) registers connected in series and controlled only by a first clock (CLK1) and a second clock (CLK2), generating corresponding driving pulses in turn in response to a start pulse (STP). Each shift register comprises a pulse generation unit with a first clock input terminal receiving one of the first (AT) and the second clocks (BT) and a first power terminal (P1) coupled to a first power voltage (VDD), and a leakage protection unit coupled to the pulse generation unit, electrically separating the first power voltage from the received clock at the first clock input terminal.