公开(公告)号：JP2009152397A

公开(公告)日：2009-07-09

申请号：JP2007329003

申请日：2007-12-20

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： YANAGIDA MIYUKI ,  YAMAGUCHI KOICHI ,  IGARASHI KATSUHIKO ,  SOMA IZURU

IPC: H01C7/10

Abstract: PROBLEM TO BE SOLVED: To provide a varistor mountable in high density, having an excellent varistor characteristics, and sufficiently reducing variations in resistance value. SOLUTION: This varistor 1 has a varistor element body 10, external electrodes 30a and 30b and a resistor 60 on a main surface 10a of the varistor element body 10. The resistor 60 connects the external electrodes 30a and 30b. The varistor element body 10 includes praseodymium and/or its oxide, Ca oxide and Si oxide as a sub-component with zinc oxide as a main component. The ratio X of the Ca oxide in terms of Ca atoms to the main component of 100 mole and the ratio Y of the Si oxide in terms of Si atoms to the zinc oxide, satisfy formula (1)-(3). The resistor contains the oxide, and the external electrodes contain an oxide different from bismuth oxide. The formula (1) is 0.01≤X COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了提供高密度安装的压敏电阻，具有优异的变阻器特性，并且充分降低了电阻值的变化。 解决方案：该压敏电阻1在可变电阻元件主体10的主表面10a上具有可变电阻元件主体10，外部电极30a和30b以及电阻器60.电阻器60连接外部电极30a和30b。 变阻器元件体10包括镨和/或其氧化物，氧化钙和氧化硅作为主要成分的副成分。 Ca原子相对于主成分为100摩尔的Ca氧化物的比X和Si原子相对于氧化锌的Si氧化物的比率Y满足式（1）〜（3）。 电阻器包含氧化物，外部电极含有不同于氧化铋的氧化物。 式（1）为0.01≤X<2原子％，式（2）为0.01≤Y<1原子％，式（3）为3≤X/Y≤20。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2008091428A

公开(公告)日：2008-04-17

申请号：JP2006268086

申请日：2006-09-29

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： SENDA NAOKI ,  SOMA IZURU ,  MATSUOKA MASARU

IPC: H01C7/10

Abstract: PROBLEM TO BE SOLVED: To provide a varistor capable of obtaining desired varistor characteristics by preventing generation of varistor characteristics on a portion other than a portion between internal electrodes. SOLUTION: In the stacked chip varistor 1, a distance D e1 between two terminal electrodes 51 and a distance D i1 between first and second internal electrodes 23, 33 satisfy a relation of 0 e1 ≤4D i1 , and a distance D e2 between the two connection conductors and the distance D i1 satisfy a relation of 0 e2 ≤4D i1 . Li is dispersed on a varistor element body 11 of the stacked chip varistor 1 from its external surface side, and a region where Li is dispersed near the external surface of the varistor element body 11 has a very high electric resistance. A varistor voltage of a region between the two terminal electrodes 51 in the varistor element body 11 and a varistor voltage of a region between the two connection conductors in the varistor element body 11 are extremely higher than a varistor voltage of a region between the first and second internal electrodes 23, 33 in the varistor element body 11. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决的问题：提供能够通过防止在内部电极之间的部分以外的部分产生压敏电阻特性来获得所需的变阻器特性的压敏电阻。 解决方案：在堆叠芯片变阻器1中，两个端子电极51之间的距离D e1 和第一和第二内部电极23,33之间的距离D i1 满足 两个连接导体之间的距离D e2 和距离D i1的关系为0 e1 ≤4D 满足0 e2 ≤4D i1 的关系。 Li从其外表面侧分散在堆叠的片式可变电阻器1的变阻器元件主体11上，并且在可变电阻元件主体11的外表面附近分散有Li的区域具有非常高的电阻。 可变电阻元件主体11中的两个端子电极51之间的区域的变阻器电压和可变电阻元件体11中的两个连接导体之间的区域的压敏电压极高，高于第一和第 可变电阻元件主体11中的第二内部电极23,33。版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2008016549A

公开(公告)日：2008-01-24

申请号：JP2006184518

申请日：2006-07-04

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： KOBAYASHI HIROKAZU ,  SOMA IZURU ,  SENDA NAOKI

IPC: H01L21/60 ,  H05K3/34

CPC classification number: H01L2224/11

Abstract: PROBLEM TO BE SOLVED: To provide an electronic component capable of improving the junction strength between a terminal electrode and a protruding electrode. SOLUTION: The electronic component 1 includes a substratum 3, the terminal electrode 5, an insulating layer 7, and the protruding electrode 9. The terminal electrode 5 is formed on the substratum 3. The insulating layer 7 is formed on the substratum 3 and the terminal electrode 5 to have at least part of the electrode 5 exposed. The protruding electrode 9 is formed on the terminal electrode 5 and is made of solder. A plurality of through-holes 13 up to the terminal electrode 5 are formed on the insulating layer 7, at a rim 8 closer to a part 6 of the electrode 5 exposed from the insulating layer 7. The protruding electrode 9 is positioned on the rim 8, so that a part of it covers the rim 8 and connected with to terminal electrode 5 through the plurality of through-holes 13. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决的问题：提供能够提高端子电极和突出电极之间的结合强度的电子部件。 解决方案：电子部件1包括基底3，端子电极5，绝缘层7和突出电极9.端子电极5形成在基底3上。绝缘层7形成在基底 3和端子电极5具有暴露的电极5的至少一部分。 突起电极9形成在端子电极5上并由焊料制成。 在绝缘层7上形成多个贯通端子电极5的贯通孔13，位于靠近从绝缘层7露出的电极5的部分6的边缘8处。突出电极9位于边缘 8，使其一部分覆盖边缘8并通过多个通孔13与端子电极5相连。版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2012094638A

公开(公告)日：2012-05-17

申请号：JP2010239764

申请日：2010-10-26

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： MATSUOKA MASARU ,  TAKEUCHI GORO ,  SOMA IZURU ,  SATO HIROYUKI ,  TAGUCHI OSAMU ,  TANAKA RYUICHI

IPC: H01C7/10

Abstract: PROBLEM TO BE SOLVED: To provide a varistor element which can suppress an occurrence of cracking in a varistor element assembly when a bonding wire is connected to an external electrode.SOLUTION: A varistor element assembly 3 reveals varistor characteristics and has a first main surface 3a and a second main surface facing each other. Surface electrodes 31, 33 are arranged on the first main surface 3a and connected with corresponding inner electrodes via through hole conductors 25, 27. An insulation layer 5 consists of glass and is arranged on the first main surface 3a and the surface electrodes 31, 33 to cover them. External electrodes 11, 13 are arranged on the insulation layer 5 and connected with the surface electrodes 31, 33. Connection position of the surface electrodes 31, 33 and the through hole conductors 25, 27 and the center C of connection position of the bonding wire in the external electrodes 11, 13 are shifted when viewed from a direction perpendicular to the first main surface 3a.

Abstract translation: 要解决的问题：提供一种当电阻线连接到外部电极时可抑制非线性电阻元件组件中的开裂发生的变阻器元件。 解决方案：变阻器元件组件3揭示了变阻器特性，并具有彼此面对的第一主表面3a和第二主表面。 表面电极31,33布置在第一主表面3a上并且经由通孔导体25,27与相应的内部电极连接。绝缘层5由玻璃构成，并且布置在第一主表面3a和表面电极31,33上 覆盖他们 外部电极11,13布置在绝缘层5上并与表面电极31,33连接。表面电极31,33和通孔导体25,27的连接位置和接合线的连接位置的中心C 当从垂直于第一主表面3a的方向观察时，外部电极11,13偏移。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2008311362A

公开(公告)日：2008-12-25

申请号：JP2007156658

申请日：2007-06-13

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： SOMA IZURU ,  SENDA NAOKI ,  MATSUOKA MASARU ,  YANAGIDA MIYUKI

IPC: H01C7/10 ,  H01G4/12 ,  H01G4/30

CPC classification number: H01G2/06 ,  H01B1/02 ,  H01B1/16 ,  H01G4/008 ,  H01G4/30

Abstract: PROBLEM TO BE SOLVED: To provide a ceramic electronic component having external electrodes excelling in solder wettability, solder corrosion resistance, impact resistance and connection reliability in a heat cycle environment. SOLUTION: A laminated chip varistor is provided with a varistor element 11, and the external electrodes 51 arranged on the varistor element 11. The external element 11 includes a first electrode layer 51a and a second electrode layer 51b. The first electrode layer 51a is formed on an outside surface of the varistor element 11, and contains Ag and a glass substance. The second electrode layer 51b is formed on the first electrode layer 51a, contains Pt, and has holes 53c reaching the first electrode layer 51a formed at a plurality of parts. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种在热循环环境中具有优异的焊料润湿性，焊料耐腐蚀性，耐冲击性和连接可靠性的外部电极的陶瓷电子部件。 解决方案：层压芯片变阻器设置有变阻器元件11，以及布置在变阻器元件11上的外部电极51.外部元件11包括第一电极层51a和第二电极层51b。 第一电极层51a形成在可变电阻元件11的外表面上，并含有Ag和玻璃物质。 第二电极层51b形成在第一电极层51a上，包含Pt，并且具有到达形成在多个部分的第一电极层51a的孔53c。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007234995A

公开(公告)日：2007-09-13

申请号：JP2006056886

申请日：2006-03-02

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： TANAKA HITOSHI ,  SOMA IZURU ,  YOSHIDA HISAYOSHI ,  TAKEHANA MAKIKAZU ,  TAKAHASHI WATARU

IPC: H01C7/10

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a laminated chip varistor capable of producing the laminated chip varistor having sufficient varistor characteristic even in the case of baking at a low temperature. SOLUTION: In the method of manufacturing the laminated chip varistor 1, mix powder obtained by mixing glass powder in the powder of a varistor material is used, so that a baking temperature in the case of baking is lowered. Moreover, in the manufacturing method, in a varistor element body obtained by baking a laminated body LS1, the quantity of Pr and Ag included in the grain boundary of grains containing ZnO as a main component is larger than the quantity of Pr and Ag included inside of the grains, high resistance in the grain boundary is obtained. Thus, the laminated chip varistor 1 having varistor characteristic sufficient for practical use is obtained even in the case of baking at a low temperature. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 解决的问题：为了提供即使在低温烘烤的情况下，也能够制造具有足够的变阻器特性的层叠片式压敏电阻的层叠片状变阻器的制造方法。 解决方案：在制造层压芯片变阻器1的方法中，使用通过将玻璃粉末混合在可变电阻材料的粉末中获得的混合粉末，使得在烘烤的情况下的烘烤温度降低。 此外，在制造方法中，在通过烧结层叠体LS1而获得的变阻器元件体中，包含在含有ZnO作为主要成分的晶粒的晶界中包含的Pr和Ag的量大于包含在内部的Pr和Ag的量 的晶粒，获得了晶界的高电阻。 因此，即使在低温下烘烤的情况下，也可以获得具有足够实用的变阻器特性的层压片式变阻器1。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006261586A

公开(公告)日：2006-09-28

申请号：JP2005080255

申请日：2005-03-18

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： ITO TOMOKAZU ,  MORITA MAKOTO ,  SOMA IZURU ,  KUDO TAKAKIYO ,  OTOMO MAKOTO

IPC: H01F41/04

Abstract: PROBLEM TO BE SOLVED: To provide a process for manufacturing a coil component easily while reducing the manufacturing cost.
SOLUTION: A magnetic substrate 100 is prepared, and a layer structure 110 of an insulation layer corresponding to first through fourth insulation layers 3, 9, 19, 29 on which a conductor pattern corresponding to first through fourth coil-like conductors is formed, and an insulation layer corresponding to fifth insulation layer 35 for protecting the conductor pattern is formed on the magnetic substrate 100. A sheet-like magnetic member MM is prepared by semi-curing a resin composition containing ferrite powder, and mounted such that the layer structure 110 is sandwiched by the magnetic member MM and the magnetic substrate 100. An intermediate body 120 including the magnetic member MM, the layer structure 110 and the magnetic substrate 100 is pressed and the magnetic member MM included in the intermediate body 120 is hardened.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种制造线圈部件的方法，同时降低制造成本。 解决方案：制备磁性基板100，并且对应于其上对应于第一至第四线圈状导体的导体图案的第一至第四绝缘层3,9,19,29的绝缘层的层结构110为 形成，并且在磁性基板100上形成对应于用于保护导体图案的第五绝缘层35的绝缘层。通过半固化含有铁氧体粉末的树脂组合物制备片状磁性构件MM，并将其安装成 层结构110被磁性部件MM和磁性基板100夹持。包括磁性部件MM，层状结构110和磁性基板100的中间体120被按压，并且包括在中间体120中的磁性部件MM被硬化 。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006237249A

公开(公告)日：2006-09-07

申请号：JP2005049358

申请日：2005-02-24

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： ITO TOMOKAZU ,  MORITA MAKOTO ,  SOMA IZURU ,  KUDO TAKAKIYO ,  OTOMO MAKOTO

IPC: H01F17/04

Abstract: PROBLEM TO BE SOLVED: To provide a coil component in which the degree of freedom is enhanced in the mixing amount of magnetic powder while ensuring adhesion of an adhesive layer.
SOLUTION: A common mode choke coil C comprises an external electrode 1 arranged with a first coil conductor 5 and a second coil conductor 7 along a first magnetic substrate MB1 and a second magnetic substrate MB2, respectively, between them and connected electrically with the first coil conductor 5 and the second coil conductor 7, a resin layer RL containing magnetic powder formed along the first coil conductor 5 and the second coil conductor 7, and a layer GL for bonding the resin layer RL and the second magnetic substrate MB2, wherein the content of magnetic powder in the resin layer RL is 88 wt% or less and the relative permeability of the resin layer RL is 4 or above.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种线圈组件，其中在确保粘合剂层的粘附的同时，在磁粉的混合量中自由度提高。 解决方案：共模扼流线圈C包括外部电极1，其外部电极1分别布置有第一线圈导体5和第二线圈导体7，沿着第一磁性基板MB1和第二磁性基板MB2分别在它们之间并与 第一线圈导体5和第二线圈导体7，包含沿着第一线圈导体5和第二线圈导体7形成的磁性粉末的树脂层RL和用于接合树脂层RL和第二磁性基板MB2的层GL， 其中，树脂层RL中的磁粉的含量为88重量％以下，树脂层RL的相对导磁率为4以上。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2008091441A

公开(公告)日：2008-04-17

申请号：JP2006268193

申请日：2006-09-29

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： SENDA NAOKI ,  SOMA IZURU ,  MATSUOKA MASARU

IPC: H01C7/10

Abstract: PROBLEM TO BE SOLVED: To provide a varistor capable of obtaining desired varistor characteristics by preventing generation of varistor characteristics on a portion other than a portion between internal electrodes. SOLUTION: Li is dispersed on a varistor element body 11 of a stacked chip varistor 1 from its external surface side. A region where Li is dispersed near the external surface of the varistor element body 11 has a very high electric resistance. Accordingly, a varistor voltage of a region between the two terminal electrodes 51 in the varistor element body 11 and a varistor voltage of a region between the two connection conductors 41 in the varistor element body 11 are extremely higher than a varistor voltage of a region between the first and second internal electrodes 23, 33 in the varistor element body 11. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 解决的问题：提供能够通过防止在内部电极之间的部分以外的部分产生压敏电阻特性来获得所需的变阻器特性的压敏电阻。 解决方案：Li从其外表面侧分散在堆叠的片式压敏电阻器1的变阻器元件主体11上。 在可变电阻元件主体11的外表面附近分散有Li的区域具有非常高的电阻。 因此，可变电阻元件主体11中的两个端子电极51之间的区域的压敏电压和可变电阻元件主体11中的两个连接导体41之间的区域的压敏电压极大地高于压敏电阻元件主体11中的区域之间的压敏电压 可变电阻元件主体11中的第一和第二内部电极23,33。版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007141953A

公开(公告)日：2007-06-07

申请号：JP2005330375

申请日：2005-11-15

Applicant: Tdk Corp ,  Tdk株式会社

Inventor： TANAKA HITOSHI ,  SOMA IZURU ,  YOSHIDA HISAYOSHI ,  TAKEHANA MAKIKAZU

IPC: H01C7/10

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a laminated chip varistor having sufficient varistor characteristics, even when subjected to low-temperature baking. SOLUTION: A baking temperature during baking is reduced so as to use mixed powder formed by mixing glass powder into varistor material powder in the method for manufacturing the laminated chip varistor 1. In addition, an amount of Pr and that of Ag existing in a grain boundary of grains mainly composed of ZnO are further increased than an amount of Pr and that of Ag existing in the grains, so as to achieve high resistance in the grain boundary in a varistor element obtained by baking a laminated body LS1 in the manufacturing method. Consequently, it is possible to obtain the laminated chip varistor 1 having practically sufficient varistor characteristics even at a low baking temperature. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：即使进行低温烘烤，也可提供具有足够的变阻器特性的层压片式压敏电阻的制造方法。 解决方案：在制造层压片式压敏电阻1的方法中，烘烤时的烘烤温度降低，从而使用通过将玻璃粉末混合在压敏电阻材料粉末中形成的混合粉末。此外，存在一定量的Pr和Ag的量 在主要由ZnO构成的晶粒的晶粒边界中，与存在于晶粒中的Ag和Ag的晶界相比进一步增加，从而在通过烧结层叠体LS1而得到的变阻器元件的晶界上实现高电阻 制造方法。 因此，即使在低的烘烤温度下，也可以获得具有实际上足够的变阻器特性的层压芯片变阻器1。 版权所有（C）2007，JPO＆INPIT