公开(公告)号：WO2014036542A1

公开(公告)日：2014-03-06

申请号：PCT/US2013/057758

申请日：2013-09-02

Applicant: TENSORCOM, INC.

Inventor： DAI, Dai

IPC: H03F3/45

CPC classification number: H03M1/0818 ,  H03M1/0809 ,  H03M1/124 ,  H03M1/365

Abstract: The core concept of this ADC is the high-speed fully-differential comparators which are clocked at 2.64 GHz and used in a 60 GHz transceiver. The comparator consists of a pre-amplifier stage, a capture stage, a regeneration cell and an output latch. The pre-amplifier stage is not clocked; therefore, the pre-amplifier stage does not suffer initialization and transient behavior effects when the clock signal switches state. The transient response of being enabled and disabled is eliminated. Instead, a capture stage transfers the contents of the pre-amplifier stage into a memory regeneration stage. The capture stage is clocked by pulses that are timed to minimize the clock kick-back generated by the memory regeneration stage. The clock kick-back is reduced even when many comparators are coupled to the PGA. The comparators are also aligned right next to each other to minimize the mismatching layout effect.

Abstract translation: 该ADC的核心概念是高速全差分比较器，时钟频率为2.64 GHz，用于60 GHz收发器。 比较器由前置放大器级，捕获级，再生单元和输出锁存器构成。 前置放大器级没有计时; 因此，当时钟信号切换状态时，前置放大器级不会受到初始化和瞬态特性的影响。 消除了启用和禁用的瞬态响应。 相反，捕获级将前置放大器级的内容传送到存储器再生级。 捕获级由定时的脉冲计时，以最小化由存储器再生阶段产生的时钟反冲。 即使许多比较器耦合到PGA，时钟反转也减少。 比较器也彼此对齐，以最小化不匹配的布局效果。

公开(公告)号：WO2014036543A1

公开(公告)日：2014-03-06

申请号：PCT/US2013/057759

申请日：2013-09-02

Applicant: TENSORCOM, INC.

Inventor： DAI, Dai

IPC: H03F3/45

CPC classification number: H03M1/0818 ,  H03M1/0809 ,  H03M1/124 ,  H03M1/365

Abstract: The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital convertors (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancelation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.

Abstract translation: 可编程增益放大器（PGA）的差分输出由多个模数转换器（ADC）比较器的输入差分栅极电容和差分金属层迹线加载，以将这些比较器与PGA互连。 提供给PGA的差分电容性负载相当大，并降低了PGA和ADC之间的这种互连的带宽。 为了克服由于差分电容性负载引起的性能下降，有源负电容电路消除了ADC比较器的大输入电容的影响。 该取消扩展了PGA输出与比较器的第一级的输入之间的互连的增益特性。 有源负电容由交叉对NMOS组成，其中电容器连接其源极，其中每个NMOS由电流源偏置。

公开(公告)号：EP2893637A1

公开(公告)日：2015-07-15

申请号：EP13832732.5

申请日：2013-09-02

Applicant: Tensorcom Inc.

Inventor： DAI, Dai

IPC: H03F3/45

CPC classification number: H03M1/0818 ,  H03M1/0809 ,  H03M1/124 ,  H03M1/365

Abstract: The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital convertors (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancelation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.