公开(公告)号：EP1102163A3

公开(公告)日：2005-06-29

申请号：EP00310098.9

申请日：2000-11-14

Applicant: Texas Instruments Incorporated

Inventor： Hoyle, David ,  Golston, Jeremiah E. ,  Zbiciak, Joseph R. ,  Markandey, Vishal ,  Simar, Jr.,Laurence R. ,  Stotzer, Eric J.

IPC: G06F15/80 ,  G06F9/302

CPC classification number: G06F9/3891 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3555 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3853 ,  G06F9/3885

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline that has several execution phases that involve fetch/decode units lOa-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Multi-field arithmetic/logic unit (ALU) circuitry (L1, L2, S1, S2) is provided for operating on a set of source operands to form a multi-field destination operand by treating the plurality of source operands as a set of N1 fields, such that the multi-field result includes N1 results corresponding to the set of N1 fields. Multi-field multiplication circuitry (M1, M2) is provided for operating on a set of source operands to form a multi-field destination operand by treating the plurality of source operands as a set of N2 fields, such that the multi-field result includes N2 results corresponding to the set of N2 fields. An instruction set architecture (ISA) is provided that is optimized for intensive numeric algorithm processing and includes a set of single instruction, multiple data (SIMD) instructions to direct the operation of the multi-field ALU circuitry and the multi-field multiplication circuitry. Non-aligned data transfer to data memory (D1, D2, 22) can be performed for byte, half word, word, and double-word data items.

Abstract translation: 在具有微处理器1和外围设备60-61的集成电路42上的数据处理系统设置有仿真单元50，其在连接到外部测试系统51时允许集成电路42的调试和仿真。微处理器1在指令执行管线 其具有涉及获取/解码单元10a-c和功能执行单元12,14,16和18的几个执行阶段。微处理器1的流水线是不受保护的，从而可以利用数据存储器22和寄存器文件20的存储器访问等待时间 存储在指令存储器23中的系统程序代码。提供多场算术/逻辑单元（ALU）电路（L1，L2，S1，S2），用于对一组源操作数进行操作，以形成多场目的地操作数， 将多个源操作数作为一组N1字段进行处理，使得多字段结果包括对应于该组N1字段的N1个结果。 提供多场乘法电路（M1，M2），用于通过将多个源操作数视为一组N2字段来操作一组源操作数以形成多场目的地操作数，使得多场结果包括 N2结果对应于一组N2场。 提供了针对密集数字算法处理进行了优化的指令集架构（ISA），并且包括一组单指令，多数据（SIMD）指令以指导多场ALU电路和多场乘法电路的操作。 可以对字节，半字，字和双字数据项执行非对齐数据传输到数据存储器（D1，D2,22）。

公开(公告)号：EP1102163A2

公开(公告)日：2001-05-23

申请号：EP00310098.9

申请日：2000-11-14

Applicant: Texas Instruments Incorporated

Inventor： Hoyle, David ,  Golston, Jeremiah E. ,  Zbiciak, Joseph R. ,  Markandey, Vishal ,  Simar, Jr.,Laurence R. ,  Stotzer, Eric J.

IPC: G06F9/302

CPC classification number: G06F9/3891 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3555 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3853 ,  G06F9/3885

Abstract: A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline that has several execution phases that involve fetch/decode units lOa-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Multi-field arithmetic/logic unit (ALU) circuitry (L1, L2, S1, S2) is provided for operating on a set of source operands to form a multi-field destination operand by treating the plurality of source operands as a set of N1 fields, such that the multi-field result includes N1 results corresponding to the set of N1 fields. Multi-field multiplication circuitry (M1, M2) is provided for operating on a set of source operands to form a multi-field destination operand by treating the plurality of source operands as a set of N2 fields, such that the multi-field result includes N2 results corresponding to the set of N2 fields. An instruction set architecture (ISA) is provided that is optimized for intensive numeric algorithm processing and includes a set of single instruction, multiple data (SIMD) instructions to direct the operation of the multi-field ALU circuitry and the multi-field multiplication circuitry. Non-aligned data transfer to data memory (D1, D2, 22) can be performed for byte, half word, word, and double-word data items.