PACKAGED SEMICONDUCTOR DEVICES FOR HIGH VOLTAGE WITH DIE EDGE PROTECTION

    公开(公告)号:US20200381322A1

    公开(公告)日:2020-12-03

    申请号:US16996742

    申请日:2020-08-18

    Abstract: In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.

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