公开(公告)号：JP2001196497A

公开(公告)日：2001-07-19

申请号：JP2000004880

申请日：2000-01-13

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SEN MEICHI ,  FEN TAISEI ,  KAN SORITSU

IPC: H01L23/12 ,  H01L21/66 ,  H01L21/82

Abstract: PROBLEM TO BE SOLVED: To provide the structure and the manufacturing method of IC on wafer level, which are useful for improving the yield of the manufacture of IC. SOLUTION: An IC structure on wafer level is formed on a semiconductor wafer and it is formed in a plurality of discrete IC blocks on the wafer. Respective IC blocks are used for forming a plurality of IC components of memory cells. Multilayer wiring structure is formed for electrically connecting the IC components in the IC blocks. For disconnecting an IC component which does not normally operate from active use, a first test and a process of restoration are conducted. This completes the, manufacture stage of a manufacture process. For disconnecting an IC block which does not normally operate from active use even in the stage of packaging, a second test and restoration are conducted.