公开(公告)号：JPH11283964A

公开(公告)日：1999-10-15

申请号：JP13949398

申请日：1998-05-21

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHANG YI-CHUN ,  KUO MING-SHENG

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To reduce CD bias, without affecting a gate oxide layer by eliminating a silicon nitride layer through anisotropic plasma etching with a mixture of tetrafluoromethane, argon, and nitrogen, with a photoresist layer as a mask. SOLUTION: On a field oxide layer 301, a gate oxide layer 302, polysilicon layers 303, 303a, and metal silicide layers 304, 304a are formed sequentially. A photoresist layer is formed in conformity with the polysilicon layer 303, 303a formed on the silicon nitride layer, covering part of the silicon nitride layer, The exposed part of the silicon nitride layer is eliminated by anisotropic plasma etching. Here, a mixture of tetrafluoromethane, argon, and nitrogen is used as an etching reactant. After removing the photoresist layer, a cap silicon nitride layer 305, 305a and a polymer layer 306, 306a are sequentially formed on the metal silicide layer 304, 304a.

公开(公告)号：GB2337026B

公开(公告)日：2000-11-08

申请号：GB9809769

申请日：1998-05-07

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHANG YI-CHUN ,  KUO MING-SHENG

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762

公开(公告)号：DE19821452B4

公开(公告)日：2005-02-17

申请号：DE19821452

申请日：1998-05-13

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHANG YI-CHUN ,  KUO MING-SHENG

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762

公开(公告)号：DE19821452A1

公开(公告)日：1999-09-23

申请号：DE19821452

申请日：1998-05-13

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHANG YI-CHUN ,  KUO MING-SHENG

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762 ,  H01L21/283 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/336

Abstract: A silicon nitride layer is anisotropically plasma etched using a mixture of tetrafluoromethane, argon and nitrogen. Etching of a silicon nitride layer, partially covered by photoresist, comprises removing the exposed layer region with a mixture of tetrafluoromethane, argon and nitrogen. Independent claims are also included for the following: (1) a polysilicon gate production method comprising successively forming a gate oxide layer, a polysilicon layer, a metal silicide layer and a silicon nitride layer partially covered by photoresist and then carrying out the above process; and (2) a shallow trench isolation production method comprising carrying out the above process, removing the photoresist and forming an insulation-filled trench in the exposed substrate portion.

公开(公告)号：NL1009202C2

公开(公告)日：1999-11-22

申请号：NL1009202

申请日：1998-05-19

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHANG YI-CHUN ,  KUO MING-SHENG

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762

公开(公告)号：GB2337026A

公开(公告)日：1999-11-10

申请号：GB9809769

申请日：1998-05-07

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHANG YI-CHUN ,  KUO MING-SHENG

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/762

Abstract: A silicon nitride layer 401 on a semiconductor substrate 400 with a photo-resist masking layer 402 is removed by anisotropic plasma etching using a mixture of tetrafluoromethane (CF 4 ), argon (Ar) and nitrogen (N 2 ). The method can be used for shallow trench isolation and for fabricating a poly-gate where the silicon nitride layer is formed on a metal silicide layer.