公开(公告)号：JP2000174022A

公开(公告)日：2000-06-23

申请号：JP34587998

申请日：1998-12-04

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHIN KATEI ,  O SHITETSU

IPC: H01L21/3205 ,  H01L21/28 ,  H01L23/544

Abstract: PROBLEM TO BE SOLVED: To form an alignment mark of good functional quality for fully utilizing alignment performance by forming a metallic wiring layer, having openings for the mark with a higher step height. SOLUTION: A polysilicon layer 302 is formed on a semiconductor substrate, and a central part of the polysilicon layer is removed to cause the substrate to be exposed. An oxide layer 306 is then formed on the substrate and is patterned to form openings 308 to expose the substrate. A W (tungsten) layer 314 is deposited on the substrate and is flattened with a WCMP (tungsten chemical-mechanical polishing) process to form W plugs 312 in the openings. A metallic wiring layer is formed on the substrate. Finally, an alignment mark pattern is formed in the metallic wiring layer.