公开(公告)号：JPH10275867A

公开(公告)日：1998-10-13

申请号：JP19130097

申请日：1997-07-16

Applicant: UNITED MICROELECTRONICS CORP

Inventor： ON EIMO

IPC: G11C17/00 ,  H01L21/8246 ,  H01L21/84 ,  H01L27/112

Abstract: PROBLEM TO BE SOLVED: To provide a ROM device in which a source/drain region is insulated from a substrate below the source/drain region by the SOI structure and no leak current flows therebetween. SOLUTION: A source/drain region 50 is insulated from a semiconductor substrate 30 below the source/drain region 50 by an SOI structure, to thereby prevent leak current from bowing therebetween. Failures caused by a diode junction between the semiconductor substrate 30 and the source/drain region 50 is prevented, to thereby improve the operating voltage. The source/drain region 50 of a MOSFET memory cell is formed out of intrinsic amorphous silicon instead of heavily-doped polysilicon. The ROM device manufacturing method is thus quite simplified.

公开(公告)号：JPH10209303A

公开(公告)日：1998-08-07

申请号：JP17682597

申请日：1997-07-02

Applicant: UNITED MICROELECTRONICS CORP

Inventor： ON EIMO

IPC: H01L21/8234 ,  H01L21/8246 ,  H01L27/088 ,  H01L27/112

Abstract: PROBLEM TO BE SOLVED: To provide a ROM device where problems such as lateral diffusion, junction leakage, drop of breakdown voltage, etc., do not occur, and provide further a manufacturing method. SOLUTION: This ROM device includes a semiconductor substrate, the first insulating layer made on the semiconductor substrate, and semiconductor layers 43a and 43b made on the first insulating layer. The semiconductor layers 43a and 43b are removed selectively so as to form a plurality of bit lines BL1 and BL2 arranged substantially in parallel in the first direction and a plurality of channel regions 50c and 50d arranged substantially in parallel in the second direction substantially orthogonal to the first direction, and the removed section forms a plurality of recesses. This ROM device further includes a plurality of second insulating layers made on those recesses, the third insulating layer covering the semiconductor layers 43a and 43b and those second insulating layers, and a plurality of conductive layers made on the third insulating layer and arranged substantially in parallel. Those conductive layers are arranged on the above channel regions 50c and 50d, substantially in the second direction.

公开(公告)号：JPH10209301A

公开(公告)日：1998-08-07

申请号：JP20781597

申请日：1997-08-01

Applicant: UNITED MICROELECTRONICS CORP

Inventor： ON EIMO

IPC: H01L21/8246 ,  H01L27/112

Abstract: PROBLEM TO BE SOLVED: To improve the gap fill-up property and surface flatness of a wafer, by providing a grid-like structure having first parts functioning as bit lines of an ROM device and second parts functioning as channel region associated with the bit lines. SOLUTION: A photo resist layer is applied to the entire top surface of a wafer and selectively removed to expose first parts 49a, 49b of a grid-like structure other parts of which cover second parts 50a, 50f of the grid-like structure and fourth insulation layer 48. An ion implanting step is applied to diffuse a first type impurity material in the exposed parts of the grid-like structure, functioning as bit lines of an ROM device, resulting in change to more conductive n diffused regions, and a photo resist layer is removed to attain a superior planarized wafer surface, thereby providing a good gap fill-up property to trenches of the wafer top surface and reducing holes.