公开(公告)号：JPH1132332A

公开(公告)日：1999-02-02

申请号：JP27781397

申请日：1997-10-09

Applicant: UNITED MICROELECTRONICS CORP

Inventor： WU WEN-YI ,  PAN JYH-SHIN

IPC: H04N5/455 ,  G06F12/00 ,  G06T1/60 ,  H04N5/00 ,  H04N5/60 ,  H04N7/025 ,  H04N7/03 ,  H04N7/035 ,  H04N7/08 ,  H04N7/081 ,  H04N19/00 ,  H04N19/102 ,  H04N19/134 ,  H04N19/157 ,  H04N19/37 ,  H04N19/423 ,  H04N19/44 ,  H04N21/443 ,  H04N7/24

Abstract: PROBLEM TO BE SOLVED: To provide an adaptive selection method by which priority control of a memory access in a motion picture experts group(MPEG) processing unit is conducted to attain a balanced use of a band width of a memory bus. SOLUTION: An MPEG processor 100 is provided with a plurality of function modules, that is an input interface 110, a CPU 120, a voice decoder 130, a video decoder 140, a voice processor 132, a video processor 142 and a memory controller 150. Each of a plurality of the modules receives memory access control to a data bus MEM-BUS by the arbitration of the memory controller 150. The access priority of the CPU 120 over the data bus MEM-BUS is maintained lower relatively except that the CPU requires execution of analysis of MPEG compression data and initial decoding of voice compression data is executed. Thus, the use of band width of a data bus is balanced between system resources 400 and then the performance of the entire system is improved.

公开(公告)号：GB2329802A

公开(公告)日：1999-03-31

申请号：GB9720236

申请日：1997-09-23

Applicant: UNITED MICROELECTRONICS CORP

Inventor： WU WEN-YI ,  PAN JYH-SHIN

IPC: H04N5/455 ,  G06F12/00 ,  G06T1/60 ,  H04N5/00 ,  H04N5/60 ,  H04N7/025 ,  H04N7/03 ,  H04N7/035 ,  H04N7/08 ,  H04N7/081 ,  H04N19/00 ,  H04N19/102 ,  H04N19/134 ,  H04N19/157 ,  H04N19/37 ,  H04N19/423 ,  H04N19/44 ,  H04N21/443 ,  H04N7/50

Abstract: An adaptive-selection method for memory access priority control in MPEG processor. The processor has functional modules that include an input interface, a CPU, an audio decoder, a video decoder, an audio processor, a video processor and a memory controller. Each of the modules gains control over the data bus via arbitration by the memory controller for accessing the memory. The access priority of the CPU to the data bus is maintained at a relatively lower level except when the CPU needs to perform parsing 330 on the MPEG compressed data and implementing the initial decoding 320 of the audio compressed data. The use of data bus bandwidth is therefore balanced among all the system resources thereby increasing the overall system performance.

公开(公告)号：DE19747864B4

公开(公告)日：2004-04-08

申请号：DE19747864

申请日：1997-10-30

Applicant: UNITED MICROELECTRONICS CORP

Inventor： WU WEN-YI ,  PAN JYH-SHIN

IPC: H04N5/455 ,  G06F12/00 ,  G06T1/60 ,  H04N5/00 ,  H04N5/60 ,  H04N7/025 ,  H04N7/03 ,  H04N7/035 ,  H04N7/08 ,  H04N7/081 ,  H04N19/00 ,  H04N19/102 ,  H04N19/134 ,  H04N19/157 ,  H04N19/37 ,  H04N19/423 ,  H04N19/44 ,  H04N21/443 ,  G06F13/18

公开(公告)号：DE19747864A1

公开(公告)日：1999-01-07

申请号：DE19747864

申请日：1997-10-30

Applicant: UNITED MICROELECTRONICS CORP

Inventor： WU WEN-YI ,  PAN JYH-SHIN

IPC: H04N5/455 ,  G06F12/00 ,  G06T1/60 ,  H04N5/00 ,  H04N5/60 ,  H04N7/025 ,  H04N7/03 ,  H04N7/035 ,  H04N7/08 ,  H04N7/081 ,  H04N19/00 ,  H04N19/102 ,  H04N19/134 ,  H04N19/157 ,  H04N19/37 ,  H04N19/423 ,  H04N19/44 ,  H04N21/443

Abstract: The method involves using an MPEG processor, which includes an input interface for receiving compressed data to generate MPEG compressed data. The input interface, CPU, A/V frequency decoder, A/V frequency processor, memory controller and memory are connected to, and transfer data on, the data bus. The selecting method involves the steps: 1) If the CPU is to decode audio frequency, then promote the picking priority of the CPU to bus. 2) After decoding audio frequency, reduce the promoted priority. 3) If CPU is to disassemble the MPEG compressed data, then promote the picking priority of the CPU to bus. 4) Use CPU to disassemble MPEG compressed data to initially decode video frequency compressed data, then reduce the promoted priority.

公开(公告)号：GB2329802B

公开(公告)日：1999-08-18

申请号：GB9720236

申请日：1997-09-23

Applicant: UNITED MICROELECTRONICS CORP

Inventor： WU WEN-YI ,  PAN JYH-SHIN

IPC: H04N5/455 ,  G06F12/00 ,  G06T1/60 ,  H04N5/00 ,  H04N5/60 ,  H04N7/025 ,  H04N7/03 ,  H04N7/035 ,  H04N7/08 ,  H04N7/081 ,  H04N19/00 ,  H04N19/102 ,  H04N19/134 ,  H04N19/157 ,  H04N19/37 ,  H04N19/423 ,  H04N19/44 ,  H04N21/443 ,  H04N7/50

公开(公告)号：NL1007453C2

公开(公告)日：1999-05-07

申请号：NL1007453

申请日：1997-11-05

Applicant: UNITED MICROELECTRONICS CORP

Inventor： WU WEN-YI ,  PAN JYH-SHIN

IPC: H04N5/00 ,  H04N7/26 ,  H04N7/50 ,  G06F12/02

Abstract: The method involves using an MPEG processor, which includes an input interface for receiving compressed data to generate MPEG compressed data. The input interface, CPU, A/V frequency decoder, A/V frequency processor, memory controller and memory are connected to, and transfer data on, the data bus. The selecting method involves the steps: 1) If the CPU is to decode audio frequency, then promote the picking priority of the CPU to bus. 2) After decoding audio frequency, reduce the promoted priority. 3) If CPU is to disassemble the MPEG compressed data, then promote the picking priority of the CPU to bus. 4) Use CPU to disassemble MPEG compressed data to initially decode video frequency compressed data, then reduce the promoted priority.