公开(公告)号：JP2000349281A

公开(公告)日：2000-12-15

申请号：JP15531199

申请日：1999-06-02

Applicant: UNITED MICROELECTRONICS CORP

Inventor： CHEN CHIN-RAI ,  RIN TONII ,  CHOU JI-UEN

IPC: H01L29/78 ,  H01L27/08

Abstract: PROBLEM TO BE SOLVED: To lessen a parasitic capacitance between a gate and a drain and another parasitic capacitance between a gate and a source, by a method wherein a MOS transistor with a side slot is provided between a dielectric layer and the left side or right side of a conductive layer located under a metal silicide layer. SOLUTION: A substrate wafer 33, a drain 34, and a source 36 located apart from the drain 34 in a different region on a surface layer are formed on a substrate 31, and an insulating layer 38 is formed on the surface of the substrate 31 between the drain 34 and the source 36. The drain 34, source 36, and metal silicide layer 38 of the gate 40 are covered with a dielectric layer 50, and the dielectric layer 50 is made to function as an insulating layer outside a MOS transistor 29. The MOS transistor 29 is located so as to position two empty side slots 52 on lateral sides of the conductive layer 42 and between the conductive layer 42 and an upper part 44 below the dielectric layer 50 and the metal silicide layer 48.