公开(公告)号：JPH11308089A

公开(公告)日：1999-11-05

申请号：JP18760898

申请日：1998-07-02

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SE KENKO ,  RYU SHUNFU ,  BAKU ANAN

IPC: H01L21/8238 ,  H01L27/092 ,  H03K19/003 ,  H03K19/0175

Abstract: PROBLEM TO BE SOLVED: To dissolve a problem regarding an allowable range of voltages for different biased voltages by holding the difference between an output pad and gate bias of a PMOS gate transistor to be lower than the threshold voltage of the PMOS gate transistor. SOLUTION: When both a PMOS transistor 33 and an NMOS transistor 34 are turned on by a driver 32, an enable signal is set to high. Thus, an NMOS transistor 39 is turned on. When the PMOS transistor 33 and the NMOS transistor 34 are turned off by the driver 32, the enable signal is set to low. The NMOS transistor 39 is turned off and at this time, a node B is provided with the same voltage as that of a node A via a coupling resistance R. Next, a PMOS transistor 36 is turned off. In this case, a node S is held nearly at the same voltage as the voltage obtained by subtracting the threshold voltage of an NMOS transistor 35 from 3.3 volt.