公开(公告)号：JPH10256502A

公开(公告)日：1998-09-25

申请号：JP6024397

申请日：1997-03-14

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SON SEII

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/321 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a DRAM capacitor. SOLUTION: A polysilicon layer is patterned to form a bottom 30 of a capacitor connected to corresponding source/drain regions. A silicon oxide layer 32 is laminated to cover the bottom of the capacitor, photolithography is performed to provide a plurality of openings through the bottom of the capacitor from the layer 32. Polysilicon is deposited to fill each of the openings and chemical mechanical polishing is performed to remove excess polysilicon using the silicon oxide layer as a polish stop. The layer 32 is stripped to leave the capacitor bottom plates with fins or posts extending vertically from the bottom plate. A capacitor dielectric is then formed over the capacitor bottom electrodes, capacitor upper electrodes are formed, and further processing continues in the conventional manner.

公开(公告)号：JPH10321814A

公开(公告)日：1998-12-04

申请号：JP12124297

申请日：1997-05-12

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SON SEII ,  YU SUIYO

IPC: H01L21/3205 ,  H01L21/306 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a DRAM forming method which enables high productivity and high reliability. SOLUTION: A silicon nitride etch stopping layer 90 is bonded onto an entire structure of a device, including first and second source/drain regions 80 and 84 which have been exposed during a spacer etch process, followed by further bonding of a thick oxide layer 96 thereon. By performing chemicomechanical polishing, the surface of the thick oxide layer 96 is planarized. An opening is formed in the thick oxide layer 96 above the first source/drain region 84 so as to be stopped by the etch stopping layer 90. Thereafter, the etch stopping layer 90 within the opening of the thick oxide layer 96 is removed to form a capacitor electrode 98 therein, so as to be in contact with the exposed portion of the first source/drain region 84. Similarly, a bit line contact for the device may be formed.

公开(公告)号：JPH10242272A

公开(公告)日：1998-09-11

申请号：JP18140797

申请日：1997-07-07

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SON SEII

IPC: H01L23/522 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To form a metal interconnection structure having a resistivity at a uniform and predictable level by providing a conductive layer adjacent a first insulation layer on a semiconductor substrate and depositing an etching stopper layer different from the first insulation layer on the top surfaces of the conductive layer and first insulation layer. SOLUTION: The method comprises forming a metal wiring 32 having an upper surface substantially coplanar to the surface of a dielectric layer 30, forming an etching stopper layer 34 to cover the device surface and exposure regions on the surfaces of a first level metal wiring layer 32 and dielectric layer 30, depositing an intermetallic dielectric layer 36 on the stopper layer 34, forming vias through the dielectric layer 36, etching the vias, depositing a glue layer 40 to cover the dielectric layer 36 surface and vias, forming metal plugs 42 in the vias to contact the layer 40, thereby forming a metal interconnection structure having a resistivity at a uniform and predictable level.