公开(公告)号：JPH10209397A

公开(公告)日：1998-08-07

申请号：JP1196497

申请日：1997-01-07

Applicant: UNITED MICROELECTRONICS CORP

Inventor： SHI WAY SAN ,  TORI RAN YUU ,  UOOTAA RUU

IPC: H01L27/04 ,  H01L21/205 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To enhance a DRAM in capacitance using an HSG-Si layer in a process where the memory electrode of the DRAM is formed. SOLUTION: The capacitor of a DRAM cell is formed through such a manner that a doped polysilicon layer 30 is evaporated and then patterned so as to limit a lower electrode in breadth, and a hemispherical grained silicon(HSG-Si) first layer is formed on the doped polysilicon layer 30. The growth of the HSG-Si first layer is stopped, and then an HSG-Si second layer is grown. The growth of HSG-Si first layer is stopped by cooling down an evaporation substrate or by stopping evaporation for a certain time, and then evaporation is restarted for forming the HSG-Si second layer on the surface of the electrode. If the growth of the HSG-Si second layer is separately carried out independent of that of the HSG-Si first layer, the growth of the HSG-Si first layer may be interrupted by either cooling or suspending.