公开(公告)号：US09773922B1

公开(公告)日：2017-09-26

申请号：US15336819

申请日：2016-10-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Hsieh Lin ,  Chia-Fu Hsu ,  Bei-Zhun Syu

IPC: H01L27/115 ,  H01L29/792 ,  H01L29/10 ,  H01L29/78 ,  H01L27/1158

CPC classification number: H01L29/7827 ,  H01L27/1158 ,  H01L27/11582 ,  H01L29/1037 ,  H01L29/7926

Abstract: A memory device includes: a substrate; a channel layer on the substrate, in which the channel layer includes a T-shape having a horizontal portion with a first end and a second end and a vertical portion having a third end; a gate structure on a side of the vertical portion; an oxide-nitride-oxide (ONO) layer between the gate structure and the vertical portion; a source region on the first end of the horizontal portion; and a drain region on the third end of the vertical portion.