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    FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF 有权
    场效应晶体管及其制造方法

    公开(公告)号：US20150171194A1

    公开(公告)日：2015-06-18

    申请号：US14636430

    申请日：2015-03-03

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tong-Yu Chen ,  Chih-Jung Wang

    IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28

    CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/42344 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/792

    Abstract: A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.

    Abstract translation: 提供场效应晶体管（FET）及其制造方法。 FET包括衬底，鳍片凸块，绝缘层，电荷俘获结构和栅极结构。 翅片凸块设置在基板上。 绝缘层设置在基板上并且位于散热片凸块的两侧。 电荷捕获结构设置在绝缘层上并位于散热片凸块的至少一侧。 电荷捕获结构的横截面为L形。 栅极结构覆盖鳍片凸起和电荷俘获结构。

    FIELD EFFECT TRANSISTOR WITH FIN STRUCTURE
    6.
    发明申请
    FIELD EFFECT TRANSISTOR WITH FIN STRUCTURE 审中-公开
    具有结构的场效应晶体管

    公开(公告)号：US20140374841A1

    公开(公告)日：2014-12-25

    申请号：US14483165

    申请日：2014-09-11

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Jung Wang ,  Tong-Yu Chen

    IPC: H01L29/78 ,  H01L29/06

    CPC classification number: H01L29/7851 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66818

    Abstract: A FET with a fin structure includes a substrate, an isolation structure and a gate structure. The substrate includes at least one fin structure. The fin structure includes two source/drain regions and a gate channel region between the two source/drain regions. The isolation structure is disposed on the substrate and surrounds the fin structure to expose an upper portion of the fin structure. A width of the gate channel region of the exposed upper portion of the fin structure is less than each of widths of the source region and the drain region. A gate structure covering two sidewalls of the gate channel region of the exposed upper portion of the fin structure is formed. Two sidewalls of the gate structure contact two facing sidewalls of the two source/drain regions, respectively.

    Abstract translation: 具有翅片结构的FET包括衬底，隔离结构和栅极结构。 衬底包括至少一个翅片结构。 鳍结构包括两个源极/漏极区域和两个源极/漏极区域之间的栅极沟道区域。 隔离结构设置在基板上并且围绕翅片结构以暴露翅片结构的上部。 翅片结构的暴露的上部的栅极沟道区域的宽度小于源极区域和漏极区域的宽度。 形成覆盖翅片结构的暴露的上部的栅极沟道区的两个侧壁的栅极结构。 栅极结构的两个侧壁分别与两个源极/漏极区的两个相对的侧壁接触。

    PATTERNED STRUCTURE OF SEMICONDUCTOR DEVICE
    8.
    发明申请
    PATTERNED STRUCTURE OF SEMICONDUCTOR DEVICE 审中-公开
    半导体器件的图案结构

    公开(公告)号：US20150179652A1

    公开(公告)日：2015-06-25

    申请号：US14639994

    申请日：2015-03-05

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Chih-Jung Wang ,  Tong-Yu Chen

    IPC: H01L27/11 ,  H01L21/28 ,  H01L21/3213

    CPC classification number: H01L27/11 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/3213 ,  H01L21/823431 ,  H01L21/845

    Abstract: A patterned structure of a semiconductor device includes a substrate, at least a first patterned structure, and at least a second patterned structure. The first patterned structure is a single-layered structure, and the second patterned structure is a multi-layered structure. The width of the second patterned structure is greater than the width of the first patterned structure.

    Abstract translation: 半导体器件的图案化结构包括至少第一图案化结构和至少第二图案化结构的衬底。 第一图案结构是单层结构，第二图案结构是多层结构。 第二图案化结构的宽度大于第一图案化结构的宽度。

    Method of Forming Trench in Semiconductor Substrate
    9.
    发明申请
    Method of Forming Trench in Semiconductor Substrate 有权
    半导体基板中形成沟槽的方法

    公开(公告)号：US20150111385A1

    公开(公告)日：2015-04-23

    申请号：US14582210

    申请日：2014-12-24

    Applicant: UNITED MICROELECTRONICS CORP.

    Inventor： Tong-Yu Chen ,  Chih-Jung Wang

    IPC: H01L21/768 ,  H01L21/311

    CPC classification number: H01L21/76807 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/28132 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/311 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L29/66795

    Abstract: The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.

    Abstract translation: 本发明提供一种在半导体衬底中形成沟槽的方法。 首先，在半导体衬底上形成第一图案化掩模层。 第一图案化掩模层具有第一沟槽。 然后，沿着第一沟槽形成材料层。 然后，在材料层上形成第二图案化掩模层以完全填充第一沟槽。 当保持第二图案化掩模层和半导体衬底之间的材料层的部分以形成第二沟槽时，去除材料层的一部分。 最后，通过使用第一图案化掩模层和第二图案化掩模层作为掩模来执行蚀刻工艺。

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