公开(公告)号：US10134858B2

公开(公告)日：2018-11-20

申请号：US15493154

申请日：2017-04-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tian Choy Gan ,  Chu-Yun Hsiao ,  Chun-Che Huang ,  Chia-Fu Hsu

IPC: H01L29/06 ,  H01L29/40 ,  H01L23/535 ,  H01L29/423 ,  H01L21/762 ,  H01L21/768 ,  H01L21/02

Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

公开(公告)号：US20160300755A1

公开(公告)日：2016-10-13

申请号：US14711777

申请日：2015-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tian Choy Gan ,  Chu-Yun Hsiao ,  Chun-Che Huang ,  Chia-Fu Hsu

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/423 ,  H01L21/768

CPC classification number: H01L29/4236 ,  H01L21/02274 ,  H01L21/76224 ,  H01L21/7684 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42384

Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

Abstract translation: 半导体工艺包括以下步骤。 在电介质层的沟槽中依次形成金属栅极条和盖层。 切割盖层和金属栅极条以在多个金属栅极上形成多个盖，并且间隙隔离相邻的盖和相邻的金属栅。 隔离材料填补了间隙。 本发明还提供了由所述半导体工艺形成的半导体结构。 例如，半导体结构在电介质层的沟槽中包括多个堆叠结构，其中每个堆叠结构在金属栅极上包括金属栅极和盖子，其中隔离槽在端部隔离并接触相邻堆叠结构 结束，并且隔离槽具有与堆叠结构相同的水平。

公开(公告)号：US20170222003A1

公开(公告)日：2017-08-03

申请号：US15493154

申请日：2017-04-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tian Choy Gan ,  Chu-Yun Hsiao ,  Chun-Che Huang ,  Chia-Fu Hsu

IPC: H01L29/423 ,  H01L23/535 ,  H01L21/02 ,  H01L29/06 ,  H01L21/768 ,  H01L21/762

CPC classification number: H01L29/4236 ,  H01L21/02274 ,  H01L21/76224 ,  H01L21/7684 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42384

Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

公开(公告)号：US09666471B2

公开(公告)日：2017-05-30

申请号：US14711777

申请日：2015-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tian Choy Gan ,  Chu-Yun Hsiao ,  Chun-Che Huang ,  Chia-Fu Hsu

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L21/762 ,  H01L21/768 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/4236 ,  H01L21/02274 ,  H01L21/76224 ,  H01L21/7684 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/401 ,  H01L29/42384

Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.