公开(公告)号：US11271078B2

公开(公告)日：2022-03-08

申请号：US16836953

申请日：2020-04-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

公开(公告)号：US10388788B2

公开(公告)日：2019-08-20

申请号：US15636632

申请日：2017-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu ,  Kuo-Chin Hung

IPC: H01L29/78 ,  H01L21/768 ,  H01L23/522 ,  H01L29/45

Abstract: A method for forming a semiconductor device is disclosed. A p-type field-effect transistor (p-FET) is formed on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate and completely covers the p-FET. At least an opening is formed in the dielectric layer and exposes a source/drain region of the p-FET. A conductive material is then formed filling the opening, wherein the conductive material comprises a first stress; specifically, a tensile stress between 400 and 800 MPa.

公开(公告)号：US11664425B2

公开(公告)日：2023-05-30

申请号：US17580622

申请日：2022-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

CPC classification number: H01L29/105 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26533 ,  H01L21/324 ,  H01L21/823412 ,  H01L29/1054 ,  H01L29/6659 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/7833

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US10651275B2

公开(公告)日：2020-05-12

申请号：US15893681

申请日：2018-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US20190214465A1

公开(公告)日：2019-07-11

申请号：US15893681

申请日：2018-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US20220140080A1

公开(公告)日：2022-05-05

申请号：US17580622

申请日：2022-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US20200235208A1

公开(公告)日：2020-07-23

申请号：US16836953

申请日：2020-04-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A p-type field effect transistor (pFET) includes a gate structure on a substrate, a channel region in the substrate directly under the gate structure, and a source/drain region adjacent to two sides of the gate structure. Preferably, the channel region includes a top portion and a bottom portion, in which a concentration of germanium in the bottom portion is lower than a concentration of germanium in the top portion and a depth of the top portion is equal to a depth of the bottom portion.

公开(公告)号：US20180342618A1

公开(公告)日：2018-11-29

申请号：US15636632

申请日：2017-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu ,  Kuo-Chin Hung

IPC: H01L29/78 ,  H01L21/768 ,  H01L23/522 ,  H01L29/45

CPC classification number: H01L29/7845 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53209 ,  H01L29/41791 ,  H01L29/456 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for forming a semiconductor device is disclosed. A p-type field-effect transistor (p-FET) is formed on a semiconductor substrate. A dielectric layer is formed on the semiconductor substrate and completely covers the p-FET. At least an opening is formed in the dielectric layer and exposes a source/drain region of the p-FET. A conductive material is then formed filling the opening, wherein the conductive material comprises a first stress; specifically, a tensile stress between 400 and 800 MPa

公开(公告)号：US10043669B2

公开(公告)日：2018-08-07

申请号：US15412066

申请日：2017-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shao-Ping Chen

IPC: H01L21/336 ,  H01L29/165 ,  H01L21/28 ,  H01L29/49 ,  H01L21/22 ,  H01L21/38 ,  H01L29/51 ,  H01L21/02

CPC classification number: H01L29/517 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/28088 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/515 ,  H01L29/518

Abstract: A method for fabricating a metal gate structure includes following steps. A substrate is provided and followed by forming a high-K dielectric layer on the substrate. Then, an oxygen-containing titanium nitride layer is formed on the high-K dielectric layer. Next, an amorphous silicon layer is formed on the oxygen-containing titanium nitride layer and followed by performing an annealing process to drive oxygen in the oxygen-containing titanium nitride layer to the high-K dielectric layer.

公开(公告)号：US20180190499A1

公开(公告)日：2018-07-05

申请号：US15412066

申请日：2017-01-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shao-Ping Chen

IPC: H01L21/28

CPC classification number: H01L21/28185 ,  H01L21/02326 ,  H01L21/28088 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/515 ,  H01L29/517 ,  H01L29/518

Abstract: A method for fabricating a metal gate structure includes following steps. A substrate is provided and followed by forming a high-K dielectric layer on the substrate. Then, an oxygen-containing titanium nitride layer is formed on the high-K dielectric layer. Next, an amorphous silicon layer is formed on the oxygen-containing titanium nitride layer and followed by performing an annealing process to drive oxygen in the oxygen-containing titanium nitride layer to the high-K dielectric layer.