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公开(公告)号:US20240079478A1
公开(公告)日:2024-03-07
申请号:US18344625
申请日:2023-06-29
Inventor: Guangwei XU , Qiming HE , Xuanze ZHOU , Qiuyan LI , Xiaolong ZHAO , Shibing LONG
IPC: H01L29/66 , H01L21/477 , H01L29/872
CPC classification number: H01L29/66969 , H01L21/477 , H01L29/872
Abstract: A preparation method of a gallium oxide device based on high-temperature annealing technology and a gallium oxide device are provided. The preparation method includes: preparing a first barrier layer on a surface of a gallium oxide wafer to block an oxygen atmosphere; implementing a patterning process for regulating impurities of the gallium oxide wafer on the barrier layer, a process depth of the patterning process not exceeding a thickness of the barrier layer; annealing the gallium oxide wafer subjected to above treatment in the oxygen atmosphere; removing the barrier layer; and removing a surface layer of the gallium oxide wafer with the barrier layer lifted off. Problems that a local region of a gallium oxide material cannot be treated alone and net carrier concentration in a selective region of the gallium oxide material cannot be regulated with high-temperature annealing technology in the oxygen atmosphere in related art are solved.
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公开(公告)号:US20240079477A1
公开(公告)日:2024-03-07
申请号:US18216425
申请日:2023-06-29
Inventor: Xuanze ZHOU , Guangwei XU , Shibing LONG
IPC: H01L29/66 , H01L21/425 , H01L21/443 , H01L21/465 , H01L21/477 , H01L29/24 , H01L29/786
CPC classification number: H01L29/66969 , H01L21/425 , H01L21/443 , H01L21/465 , H01L21/477 , H01L29/24 , H01L29/78642 , H01L29/7869
Abstract: A vertical gallium oxide transistor and a preparation method thereof are provided. The method includes: annealing a gallium oxide material in an oxygen atmosphere at a range of temperature of 1000 to 1400° C. for 1 to 24 h so as to form a single crystal layer, a defective layer and an oxidized layer; removing the defective layer and the oxidized layer on a back of the gallium oxide material and the defective layer on a front of the gallium oxide material so as to obtain an initial sample; and preparing a heavily doped contact layer on the oxidized layer, preparing a source electrode layer on the contact layer, and preparing a trench perpendicular to a plane of the sample, and preparing a gate dielectric layer in the trench to fabricate a gate electrode and a drain electrode.
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