公开(公告)号：US12302608B2

公开(公告)日：2025-05-13

申请号：US18679459

申请日：2024-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kuang Hsieh ,  Shih-Hung Tsai ,  Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/16 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786 ,  H10D30/01 ,  H10D30/67 ,  H10D62/10 ,  H10D62/80 ,  H10D62/83 ,  H10D64/62

Abstract: A nanowire transistor includes a channel structure on a substrate, a gate structure on and around the channel structure, a source/drain structure adjacent to two sides of the gate structure, and a contact plug connected to the source/drain structure. Preferably, the source/drain structure includes graphene and the contact plug further includes a silicide layer on the source/drain structure, a graphene layer on the silicide layer, and a barrier layer on the graphene layer.

公开(公告)号：US20240264224A1

公开(公告)日：2024-08-08

申请号：US18116272

申请日：2023-03-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Jinn-Horng Lai ,  Yan-Zung Wang ,  Peng-Hsiu Chen ,  Su-Ming Hsieh

IPC: G01R31/28 ,  H01L23/485

CPC classification number: G01R31/2886 ,  H01L23/485

Abstract: A ground-signal-ground (GSG) device structure is provided in the present invention, including two signal pads aligned in a first direction and two ground pads respectively at two sides of each signal pad in a second direction, and two transmission lines between the two signal pads and are connected respectively with said two signal pads, and said two transmission lines extend toward each other in the first direction and connect to a device, wherein the two signal pads and the two transmission lines are only in the level of 7th metal layer or above in back-end-of-line (BEOL) metal layers.

公开(公告)号：US20230354716A1

公开(公告)日：2023-11-02

申请号：US18219713

申请日：2023-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Yu-Ping Wang

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/10 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

公开(公告)号：US20230090612A1

公开(公告)日：2023-03-23

申请号：US17991765

申请日：2022-11-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chun-Hsien Lin ,  Chien-Hung Chen

IPC: H01L27/11 ,  H01L27/092 ,  H01L29/08 ,  H01L29/417 ,  H01L21/8238 ,  H01L21/285 ,  H01L29/45

Abstract: A method for fabricating a static random access memory (SRAM) includes the steps of: forming a gate structure on a substrate; forming an epitaxial layer adjacent to the gate structure; forming a first interlayer dielectric (ILD) layer around the gate structure; transforming the gate structure into a metal gate; forming a contact hole exposing the epitaxial layer, forming a barrier layer in the contact hole, forming a metal layer on the barrier layer, and then planarizing the metal layer and the barrier layer to form a contact plug. Preferably, a bottom portion of the barrier layer includes a titanium rich portion and a top portion of the barrier layer includes a nitrogen rich portion.

公开(公告)号：US20210020832A1

公开(公告)日：2021-01-21

申请号：US17064606

申请日：2020-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Yu-Ping Wang

IPC: H01L43/08 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A method for fabricating semiconductor device includes the steps of first providing a substrate having a magnetic tunnel junction (MTJ) region and an edge region, forming an first inter-metal dielectric (IMD) layer on the substrate, and then forming a first MTJ and a second MTJ on the first IMD layer, in which the first MTJ is disposed on the MTJ region while the second MTJ is disposed on the edge region. Next, a second IMD layer is formed on the first MTJ and the second MTJ.

公开(公告)号：US10608045B2

公开(公告)日：2020-03-31

申请号：US16297698

申请日：2019-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Yu-Ping Wang

IPC: H01L27/22 ,  H01L23/522 ,  H01L43/02 ,  H01L23/528 ,  H01L43/08 ,  H01L43/12 ,  H01F10/32 ,  H01F41/34 ,  G11C11/16

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, first plug, a magnetoresistive random access memory (MRAM) structure, a spacer layer, a seal layer and a first conductive pattern. The substrate has a first region and a second region, and the first plug is disposed on a dielectric layer disposed on the substrate, within the first region. The MRAM structure is disposed in the dielectric layer and electrically connected to the first plug. The spacer layer is disposed both within the first region and the second region, to cover the MRAM structure. The seal layer is disposed on the MRAM structure and the first plug, only within the first region. The first conductive pattern penetrates through the seal layer to electrically connect the MRAM structure.

公开(公告)号：US10510884B2

公开(公告)日：2019-12-17

申请号：US16056564

申请日：2018-08-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chun-Hsien Lin

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/78 ,  H01L29/49 ,  H01L21/3105

Abstract: A method for fabricating a semiconductor device is disclosed. A dummy gate is formed on a semiconductor substrate. The dummy gate has a first sidewall and a second sidewall opposite to the first sidewall. A low-k dielectric layer is formed on the first sidewall of the dummy gate and the semiconductor substrate. A spacer material layer is deposited on the low-k dielectric layer, the second sidewall of the dummy gate, and the semiconductor substrate. The spacer material layer and the low-k dielectric layer are etched to form a first spacer structure on the first sidewall and a second spacer structure on the second sidewall. A drain doping region is formed in the semiconductor substrate adjacent to the first spacer structure. A source doping region is formed in the semiconductor substrate adjacent to the second spacer structure.

公开(公告)号：US20190103488A1

公开(公告)日：2019-04-04

申请号：US15723186

申请日：2017-10-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/786 ,  H01L29/417 ,  H01L29/423 ,  H01L29/10

Abstract: A semiconductor device includes a first dielectric layer on a substrate, a hard mask layer on the first dielectric layer, a trench in the hard mask layer and the first dielectric layer, a first source/drain electrode layer on a sidewall of the trench, a second dielectric layer on the first source/drain electrode layer in the trench, a second source/drain electrode layer on the second dielectric layer in the trench, a third dielectric layer on the second source/drain electrode layer in the trench, a 2D material layer overlying the hard mask layer, the first source/drain electrode layer, the second dielectric layer, the second source/drain electrode layer, and the third dielectric layer, a gate dielectric layer on the 2D material layer, and a gate electrode on the gate dielectric layer.

公开(公告)号：US10049929B2

公开(公告)日：2018-08-14

申请号：US15008453

申请日：2016-01-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Chih-Sen Huang ,  Po-Chao Tsao ,  Chieh-Te Chen

IPC: H01L21/4763 ,  H01L21/768 ,  H01L29/78 ,  H01L23/485 ,  H01L29/66 ,  H01L21/283 ,  H01L21/321 ,  H01L23/528 ,  H01L29/45 ,  H01L29/417 ,  H01L23/532 ,  H01L29/165

Abstract: The present invention provides a method of forming a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate.

公开(公告)号：US20180166441A1

公开(公告)日：2018-06-14

申请号：US15825057

申请日：2017-11-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  Kun-Yuan Liao ,  Hsiang-Hung Peng ,  Wei-Hao Huang ,  Ching-Wen Hung ,  Chih-Sen Huang

IPC: H01L27/06 ,  H01L21/8234 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L27/0629 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L28/20 ,  H01L28/24

Abstract: A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a trench isolation region, a resistor-forming region is provided. A first ILD layer covers the first region, the second region, and the resistor-forming region. A resistor material layer and a capping layer are formed over the first region, the second region, and the resistor-forming region. The capping layer and the resistor material layer are patterned to form a first hard mask pattern above the first and second regions and a second hard mask pattern above the resistor-forming region. The resistor material layer is isotropically etched. A second ILD layer is formed over the substrate. The second ILD layer and the first ILD layer are patterned with a mask and the first hard mask pattern to form a contact opening.