公开(公告)号：WO1992011638A2

公开(公告)日：1992-07-09

申请号：PCT/EP1991002386

申请日：1991-12-10

Applicant: VLSI TECHNOLOGY INC

Inventor： VLSI TECHNOLOGY INC ,  FRENKIL, Gerald, Lee ,  GOLSON, Steven, E.

IPC: G11C11/406

CPC classification number: G11C11/406

Abstract: A DRAM allows for hidden refresh of its memory cells. The refresh is performed during a refresh segment of the clock cycle. In a preferred embodiment, immediately before the beginning of each clock cycle the DRAM selects a word line for a row of memory cells for which a data access is to be performed. The DRAM also selects at least one word line for at least one row of memory cells for which a refresh is to be performed. During the refresh cycle, a refresh is performed on every memory cell row which is selected for data access or which is selected for refresh. After the refresh cycle, during a data access segment of the clock cycle, the DRAM continues to select the word line for the row of memory cells for which a data access is to be performed; however, the DRAM no longer selects the at least one word line for at the least one row of memory cells selected for refresh. During the data access segment of the clock cycle, the data access is performed on the row of memory cells which remain selected.

公开(公告)号：WO1992011643A1

公开(公告)日：1992-07-09

申请号：PCT/EP1991002330

申请日：1991-12-03

Applicant: VLSI TECHNOLOGY INC

Inventor： VLSI TECHNOLOGY INC ,  HARTOOG, Mark, R. ,  ROWSON, James, A. ,  SHUR, Robert, D. ,  VAN EGMOND, Kenneth, D.

IPC: G60F11/26

CPC classification number: G01R31/3185 ,  G06F2201/83

Abstract: An integrated circuit includes parity chains which serve as test logic. Each parity chain comprises chains of XOR gates (211, 212, 213 etc.). One input to each XOR gate after the first in a chain is connected to the output of the preceding XOR gate. The remaining inputs are connected to nodes of the main logic, thus defining test points. An error at any one of the test points is indicated in the output of the respective parity chain. The outputs of the parity chains are arranged as parallel inputs to a linear feedback shift register (370) which provides a serial signature which can be analyzed to detect defects in the integrated circuit.

公开(公告)号：WO1991006120A1

公开(公告)日：1991-05-02

申请号：PCT/EP1990001717

申请日：1990-10-08

Applicant: VLSI TECHNOLOGY INC

Inventor： VLSI TECHNOLOGY INC ,  TSOU, Morris, Hsimeng

IPC: H01L21/90

CPC classification number: H01L21/31683 ,  H01L21/28525 ,  H01L21/76889

Abstract: In a method for fabricating a semiconductor device such as a MOS device, a nitride cap (204) is formed over a remote interconnect (104) of gate material. In a subsequent oxide growth step, oxide (140) is formed over another remote interconnect (106) and transistor gates, while the nitride cap prevents oxide growth over the first remote interconnect. Thinner oxide over source and drain regions is removed, leaving oxide formations over the gates and the second interconnect; the nitride cap is also removed. Silicide (134, 136, 138) is then formed over the source and drain regions and over portions of the first remote interconnect. A conducting layer (132) is deposited and a local interconnect is then patterned therefrom which electrically connects the first remote interconnect to at least one source/drain region without using via holes. This local interconnect crosses over the second remote interconnect, while being insulated from it by the oxide formation. The result of the method is an integrated circuit device with this bridging interconnect and compact dimensions, the latter due to the relaxed tolerances afforded by the self-aligning features of the method.

公开(公告)号：WO1990016114A1

公开(公告)日：1990-12-27

申请号：PCT/EP1990000912

申请日：1990-06-11

Applicant: VLSI TECHNOLOGY INC ,  MORLON, Patrice, Pierre

Inventor： VLSI TECHNOLOGY INC

IPC: H03M01/78

CPC classification number: H03M1/0678 ,  H03M1/785

Abstract: A multiplying digital to analog converter comprises shunt legs wherein a switch (15) has a common terminal connected to a respective node (12) in the series path and two switchable terminals each connected to a respective resistor. Each series branch consists of a dummy switch (28) in series with a series resistor (13) having half the resistance value of each of the shunt resistors (14', 14''). The switches, which are preferably implemented in CMOS technology, are physically matched and the switches in the series arms are configured to be closed so that the resistance of each dummy switch is half that of the switch in the respective shunt leg. The arrangement enables the preservation of the R-2R relationship between the series and shunt resistances and thereby substantially improves the linearity of the converter.

Abstract translation: 乘法数模转换器包括分流支路，其中开关（15）具有连接到串联路径中的相应节点（12）的公共端子以及每个连接到相应电阻器的两个可切换端子。 每个串联分支包括与具有每个分流电阻器（14'，14“）的电阻值的一半的串联电阻器（13）串联的虚拟开关（28）。 优选以CMOS技术实现的开关在物理上匹配，并且串联臂中的开关被配置为闭合，使得每个虚拟开关的电阻是相应分流支路中的开关的电阻的一半。 该装置能够保持串联和分流电阻之间的R-2R关系，从而大大提高了转换器的线性度。