公开(公告)号：WO2014102530A1

公开(公告)日：2014-07-03

申请号：PCT/GB2013/053295

申请日：2013-12-13

Applicant: WOLFSON MICROELECTRONICS PLC

Inventor： MACKAY, Graeme ,  BOTHWELL, Andrew

IPC: H04R5/04 ,  G06F11/30 ,  H04M1/725

CPC classification number: H04R1/1091 ,  G06F11/3041 ,  G06F11/3051 ,  G06F11/3096 ,  H04M1/72527 ,  H04R1/1083 ,  H04R3/00 ,  H04R5/04 ,  H04R29/00 ,  H04R2201/107 ,  H04R2420/03 ,  H04R2420/05 ,  H04R2420/09

Abstract: Circuitry detects properties of an accessory removably connected thereto via a multi- pole connector. The circuitry has first, second and third circuit terminals for coupling to respective first, second, and third poles of said connector, and has an output for providing evaluation values from which properties of the accessory may be derived. In the circuitry, first current sourcing circuitry is coupled to said first circuit terminal for providing a first current. A switch network comprises first, second, third and fourth switch network terminals, said first switch network terminal coupled to a reference potential, said second switch network terminal coupled to said second circuit terminal, and said third switch network terminal coupled to said third circuit terminal. Comparator circuitry provides a comparison signal, its first input terminal being coupled to said first circuit terminal. Second current sourcing circuitry having a monitor node coupled to said second comparator input terminal and an output node coupled to said fourth switch network terminal provides a second current to said switch network. At least one of said first current sourcing circuitry and said second current-sourcing circuitry is responsive to a digital control word for varying said first or said second current. Control logic is provided for operatively controlling the state of the interconnections of said switch network, for adjusting said digital control word in response to said comparison signal until a voltage at said first circuit terminal is equal to a voltage at said monitor node, and for supplying said adjusted digital control word associated with the state of the interconnections to said output as an evaluation value.

Abstract translation: 电路检测通过多极连接器可移除地连接到其上的附件的特性。 电路具有用于耦合到所述连接器的相应第一，第二和第三极的第一，第二和第三电路端子，并且具有用于提供评估值的输出，从该值可以导出附件的属性。 在电路中，第一电流源电路耦合到所述第一电路端子，用于提供第一电流。 交换网络包括第一，第二，第三和第四交换机网络终端，所述第一交换网络终端耦合到参考电位，所述第二交换网络终端耦合到所述第二电路终端，所述第三交换网络终端耦合到所述第三电路终端 。 比较器电路提供比较信号，其第一输入端耦合到所述第一电路端。 具有耦合到所述第二比较器输入端子的监视器节点和耦合到所述第四交换机网络终端的输出节点的第二电流源电路向所述交换网络提供第二电流。 所述第一电流源电路和所述第二电流源电路中的至少一个响应数字控制字来改变所述第一或所述第二电流。 提供控制逻辑用于可操作地控制所述开关网络的互连状态，用于响应于所述比较信号调整所述数字控制字，直到所述第一电路端子处的电压等于所述监视器节点处的电压，并且用于提供 所述调整后的数字控制字与作为评估值的与所述输出的互连的状态相关联。

公开(公告)号：WO2012164272A2

公开(公告)日：2012-12-06

申请号：PCT/GB2012/051193

申请日：2012-05-25

Applicant: WOLFSON MICROELECTRONICS PLC ,  MACKAY, Graeme ,  WIGNER, Jonathan ,  MCLEOD, Gordon

Inventor： MACKAY, Graeme ,  WIGNER, Jonathan ,  MCLEOD, Gordon

IPC: H04M1/60

CPC classification number: H04M1/6025 ,  H04H60/04 ,  H04M1/72558

Abstract: An integrated circuit is used for digital signal routing. The integrated circuit has analog and digital inputs and outputs, including digital interfaces for connection to other integrated circuits. Inputs, including the digital interfaces, act as data sources. Outputs, including the digital interfaces, act as data destinations. The integrated circuit also includes signal processing blocks, which can act as data sources and data destinations. Signal routing is achieved by means of a multiply-accumulate block, which takes data from one or more data source and, after any required scaling, generates output data for a data destination. Data from a data source is buffered for an entire period of a data sample clock so that the multiply-accumulate block can retrieve the data at any point in the period, and output data of the multiply-accumulate block is buffered for an entire period of the data sample clock so that the data destination can retrieve the data at any point in the period. Multiple signal paths can be defined by configuration data supplied to the device, either by a user, or by software. The multiply-accumulate block operates on a time division multiplexed basis, so that multiple signal paths can be processed within one period of the sample clock. Each signal path has a respective sample clock rate, and paths with different sample clock rates can be routed through the multiply-accumulate block on a time division multiplexed basis independently of each other. Thus, speech signals at 8kHz or 16kHz can be processed concurrently with audio data at 44.1kHz or 48kHz.

Abstract translation: 集成电路用于数字信号路由。 集成电路具有模拟和数字输入和输出，包括用于连接到其他集成电路的数字接口。 输入，包括数字接口，作为数据源。 输出，包括数字接口，充当数据目的地。 该集成电路还包括可用作数据源和数据目的地的信号处理块。 信号路由通过乘法累加块实现，该乘法块从一个或多个数据源获取数据，并且在任何所需的缩放之后生成数据目的地的输出数据。 来自数据源的数据在数据采样时钟的整个周期中被缓冲，使得乘法累加块可以在该周期中的任何点检索数据，并且乘法累加块的输出数据被缓冲在整个周期 数据采样时钟，使得数据目的地可以在该周期的任何时间点检索数据。 多个信号路径可以由用户或软件提供给设备的配置数据来定义。 乘法累加块以时分复用为基础进行操作，从而可以在采样时钟的一个周期内处理多个信号路径。 每个信号路径具有各自的采样时钟速率，并且具有不同采样时钟速率的路径可以彼此独立地以时分复用为基础通过乘法累加块路由。 因此，可以以44.1kHz或48kHz的音频数据同时处理8kHz或16kHz的语音信号。