Abstract:
A colour detection and/or recognition apparatus comprises a twin row array (16) of detector elements, each element being arranged to produce an electrical signal on detection of a given colour. The two rows (21, 22) each comprise a plurality of groups of detector elements, with the elements in each group of at least one of the arrays being sensitive to a respective different colour, with corresponding elements in the two rows being sensitive to different colours, and with the four elements of adjacent corresponding pairs of elements in the two rows being sensitive to at least three different colours. The electrical signals are processed to provide a determination of the detection of colour or the recognition of a colour. The two rows of detector elements, typically photosensitive sites in CCD arrays, may be formed closely adjacent one another on the same semiconductor substrate, together with CCD shift registers (23, 24) along the outide edges of the two rows. A line buffer delay circuit (25) may be provided for the outputs of one of the rows.
Abstract:
A colour detection and/or recognition apparatus comprises a twin row array (16) of detector elements, each element being arranged to produce an electrical signal on detection of a given colour. The two rows (21, 22) each comprise a plurality of groups of detector elements, with the elements in each group of at least one of the arrays being sensitive to a respective different colour, with corresponding elements in the two rows being sensitive to different colours, and with the four elements of adjacent corresponding pairs of elements in the two rows being sensitive to at least three different colours. The electrical signals are processed to provide a determination of the detection of colour or the recognition of a colour. The two rows of detector elements, typically photosensitive sites in CCD arrays, may be formed closely adjacent one another on the same semiconductor substrate, together with CCD shift registers (23, 24) along the outide edges of the two rows. A line buffer delay circuit (25) may be provided for the outputs of one of the rows.