公开(公告)号：US12190994B2

公开(公告)日：2025-01-07

申请号：US18090574

申请日：2022-12-29

Applicant: XILINX, INC.

Inventor： Kumar Rahul ,  Santosh Yachareni ,  Mahendrakumar Gunasekaran ,  Mohammad Anees

IPC: G11C7/22 ,  G11C7/10

Abstract: An integrated circuitry (IC) device for a memory device includes driver circuitry, selection circuitry, clock generation circuitry, and self-time path circuitry. The driver circuitry generates a plurality of driver circuitry outputs. The selection circuitry selects one of the plurality of driver circuitry outputs based on a plurality of enable signals. The clock generation circuitry receives the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generates a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry. The self-time path circuitry of a memory receives the clock signal and generates a reset signal based on the clock signal. The plurality of driver circuitry outputs and the clock signal are based on the reset signal, and the self-time path circuitry corresponds to one or more columns of a memory bank.

公开(公告)号：US11088678B1

公开(公告)日：2021-08-10

申请号：US16788262

申请日：2020-02-11

Applicant: XILINX, INC.

Inventor： Kumar Rahul ,  Mohammad Anees ,  Mahendrakumar Gunasekaran

IPC: H03K3/356 ,  H03K3/3562 ,  H03K19/0185 ,  H03K3/037 ,  H03K3/0233

Abstract: Examples described herein generally relate to devices that include a pulsed flip-flop capable of being implemented across multiple voltage domains. In an example, a device includes a pulsed flip-flop. The pulsed flip-flop includes a master circuit and a slave circuit sequentially connected to the master circuit. The master circuit includes a pre-charge input circuit and a first latch. A first node is connected between the pre-charge input circuit and the first latch. The slave circuit includes a resolving circuit and a second latch. The first node is connected to an input node of the resolving circuit. A second node is connected between the resolving circuit and the second latch. The resolving circuit is configured to selectively (i) pull up or pull down a voltage of the second node and (ii) be disabled.