公开(公告)号：US20250077329A1

公开(公告)日：2025-03-06

申请号：US18241163

申请日：2023-08-31

Applicant: XILINX, INC.

Inventor： Zachary BLAIR ,  Alireza KHODAMORADI ,  Ralph D. WITTIG ,  Eric DELLINGER ,  Kristof DENOLF

IPC: G06F11/07 ,  G06F11/10

Abstract: A method for operating a computing system includes determining a baseline accuracy of the computing system based on a baseline data transmission format comprising a baseline quantity of data bits and a baseline quantity of error correction (ECC) bits, determining sample accuracies of the computing system based on sample data transmission formats each including a quantity of data bits and a quantity of ECC bits that are different from the baseline quantity of data bits and the baseline quantity of ECC bits, and storing data in a memory device of the computing system using at least one data transmission format, wherein the at least one data transmission format is selected from a group of data transmission formats comprising the baseline data transmission format and the sample data transmission formats and the at least one data transmission is selected based on the baseline accuracy and the sample accuracies.

公开(公告)号：US20240224542A1

公开(公告)日：2024-07-04

申请号：US18090216

申请日：2022-12-28

Applicant: XILINX, INC.

Inventor： Zachary BLAIR ,  Gabriel LOH ,  Paul HARTKE

IPC: H10B80/00 ,  H01L23/522 ,  H01L23/528

CPC classification number: H10B80/00 ,  H01L23/5223 ,  H01L23/5286

Abstract: A DRAM fabrication process for producing a semiconductor die adapted for having the ability to be both a hybrid memory and power supply capacitance. DRAM arrays on a semiconductor die may be individually selected to function as either a memory or as supplemental capacitance on a power distribution network serving circuits on one or more semiconductor dice in a three-dimensional active-on-active (AoA) stacked semiconductor die package configuration. Defective DRAM array trench capacitors can be repurposed to serve as supplemental capacitance on a power distribution network. DRAM array trench capacitors can be dynamically reassigned as supplemental capacitance when power supply monitors sense that additional power supply capacitance is needed.

公开(公告)号：US20240047364A1

公开(公告)日：2024-02-08

申请号：US17879670

申请日：2022-08-02

Applicant: XILINX, INC.

Inventor： Zachary BLAIR

IPC: H01L23/538 ,  H01L25/065 ,  G06F12/1027 ,  G06F15/78

CPC classification number: H01L23/5386 ,  H01L25/0657 ,  H01L23/5382 ,  G06F12/1027 ,  G06F15/7825 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541

Abstract: Embodiments herein describe a 3D stack of dies (e.g., an active-on-active (AoA) stack) with a connectivity die that enables the decoupling of processing regions in coupled dies from each other and from the physical location of I/O blocks on an I/O die. For example, the first die may have a plurality of hardware processing blocks that are arranged in a regular manner (e.g., an array with rows and columns). The connectivity die can include interconnects that couple these hardware processing blocks to I/O blocks in a second die. These I/O blocks may be arranged in an irregular manner. The interconnects in the connectivity die can provide fair access so that processing blocks on a first side of the first die can access an I/O block on the opposite side of the second die without using resources for neighboring processing blocks.