公开(公告)号：KR20200127241A

公开(公告)日：2020-11-10

申请号：KR20207028653

申请日：2019-03-11

Applicant: XILINX INC

Inventor： ZHUANG YI ,  LIN WINSON ,  NAMKOONG JINYUNG ,  IM HSUNG JAI ,  CHEN STANLEY Y

IPC: H03L7/08 ,  G06F1/06 ,  H03K19/0175 ,  H03K19/20 ,  H03L7/081 ,  H04L7/00 ,  H04L7/033

Abstract: 집적회로에서신호를수신하기위한회로가설명된다. 회로는, 입력데이터신호를수신하도록구성된샘플러(202) - 샘플러는샘플링된데이터및 복원된클록을생성함 -; 샘플링된데이터및 복원된클록을수신하고위상보간기코드를생성하도록구성된클록및 데이터복원회로(204); 및위상보간기코드를수신하도록구성된위상보간기(206)를포함하며, 여기서위상보간기는클록사이클에대해생성된위상보간기코드에기반하여클록사이클동안다수의위상보간기제어신호들을생성한다.

公开(公告)号：CA2713153C

公开(公告)日：2014-02-11

申请号：CA2713153

申请日：2009-02-20

Applicant: XILINX INC

Inventor： IM HSUNG JAI ,  PAAK SUNHOM ,  ANG BOON YONG

IPC: H01L23/525 ,  G11C17/16 ,  H01L27/10

Abstract: At least one MOS parameter of a MOS fuse (200) is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse (200) is programmed by applying a programming signal to the fuse terminals (204, 206) so that programming current flows through the fuse link (202). The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.

公开(公告)号：HK1132377A1

公开(公告)日：2010-02-19

申请号：HK09112289

申请日：2009-12-30

Applicant: XILINX INC

Inventor： PAAK SUNHOM ,  IM HSUNG JAI ,  ANG BOON YONG

IPC: G11C20060101 ,  H01L20060101

Abstract: A memory cell with a logic bit has a first one-time-programmable ("OTP") memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element.

公开(公告)号：CA2666120A1

公开(公告)日：2008-05-15

申请号：CA2666120

申请日：2007-10-25

Applicant: XILINX INC

Inventor： PAAK SUNHOM ,  IM HSUNG JAI ,  ANG BOON YONG

IPC: H01L21/8246 ,  G11C17/16 ,  H01L23/525 ,  H01L27/105 ,  H01L27/112 ,  H01L27/118

Abstract: A memory cell with a logic bit has a first one-time-programmable ("OTP") memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operato r coupled to the first OTP memory element output and to the second OTP memor y element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element. Examples of the memory eleme nts are polysilicon fuses having necks of different width, metsl fuses, and antifuses.

公开(公告)号：CA2666120C

公开(公告)日：2010-09-14

申请号：CA2666120

申请日：2007-10-25

Applicant: XILINX INC

Inventor： PAAK SUNHOM ,  IM HSUNG JAI ,  ANG BOON YONG

IPC: H01L21/8246 ,  G11C17/16 ,  H01L23/525 ,  H01L27/105 ,  H01L27/112 ,  H01L27/118

Abstract: A memory cell with a logic bit has a first one-time-programmable ("OTP") memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element. Examples of the memory elements are polysilicon fuses having necks of different width, metsl fuses, and antifuses.

公开(公告)号：CA2713153A1

公开(公告)日：2009-09-11

申请号：CA2713153

申请日：2009-02-20

Applicant: XILINX INC

Inventor： IM HSUNG JAI ,  PAAK SUNHOM ,  ANG BOON YONG

IPC: H01L23/525 ,  G11C17/16 ,  H01L27/10

Abstract: At least one MOS parameter of a MOS fuse (200) is characterized to provide at least one MOS parameter reference value. Then, the MOS fuse (200) is programmed by applying a programming signal to the fuse terminals (204, 206) so that programming current flows through the fuse link (202). The fuse resistance is measured to provide a measured fuse resistance associated with a first logic value. A MOS parameter of the programmed MOS fuse is measured to provide a measured MOS parameter value. The measured MOS parameter value is compared to the reference MOS parameter value to determine a second logic value of the MOS fuse, and a bit value is output based on the comparison.

公开(公告)号：WO2008057257A3

公开(公告)日：2008-07-10

申请号：PCT/US2007022657

申请日：2007-10-25

Applicant: XILINX INC

Inventor： PAAK SUNHOM ,  IM HSUNG JAI ,  ANG BOON YONG

IPC: H01L21/8246 ,  G11C17/16 ,  H01L23/525 ,  H01L27/105 ,  H01L27/112 ,  H01L27/118

CPC classification number: G11C17/18 ,  H01L23/5252 ,  H01L23/5256 ,  H01L27/101 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/11807 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory cell with a logic bit has a first one-time-programmable ("OTP") memory element providing a first OTP memory element output and a second OTP memory element providing a second OTP memory element output. A logic operator coupled to the first OTP memory element output and to the second OTP memory element output and provides a binary memory output of the memory cell. In a particular embodiment, the first OTP memory element is a different type of OTP memory than the second OTP memory element. Examples of the memory elements are polysilicon fuses having necks of different width, metsl fuses, and antifuses.

Abstract translation: 具有逻辑位的存储器单元具有提供第一OTP存储器元件输出的第一个一次可编程（“OTP”）存储器元件和提供第二OTP存储器元件输出的第二OTP存储器元件。 耦合到第一OTP存储器元件输出和第二OTP存储器元件输出的逻辑运算器，并且提供存储器单元的二进制存储器输出。 在特定实施例中，第一OTP存储器元件是与第二OTP存储器元件不同的类型的OTP存储器。 存储元件的实例是具有不同宽度的颈部，metsl保险丝和反熔丝的多晶硅保险丝。