公开(公告)号：JPH09181599A

公开(公告)日：1997-07-11

申请号：JP21752796

申请日：1996-08-19

Applicant: XILINX INC

Inventor： SUTEFUAN EMU TORIMUBAAGAA ,  RICHIYAADO EI KAABERII ,  ROBAATO ANDAASU JIYONSON ,  JIENIFUAA UON

IPC: G11C11/401 ,  G06F15/78 ,  G06F17/50 ,  H03K19/173 ,  H03K19/177

Abstract: PROBLEM TO BE SOLVED: To respecify the formats of a format specification enabled logic block and a matrix with a programmable route by preparing plural programmable logic elements and including plural memory cells for specifying a combination element format and an order logic element format in the logic elements. SOLUTION: A bit group 200 has eight memory cells MC0 to MC7 and each memory cell MC has a latch 201 and a selecting transistor(TR) 202 related to the latch 201. The memory cells MC0 to MC7 are connected to a common bit line 203 for supplying a signal to a latch 204 to be driven by a clock. All configuration bits (e.g. a 3rd configuration bit stored in a latch 2012 by the memory cell MC2) on the same position of different bit groups are included in a single slice of a memory and correspond to the single configuration (format) of an array.