公开(公告)号：JPS62117192A

公开(公告)日：1987-05-28

申请号：JP21559186

申请日：1986-09-12

Applicant: Xilinx Inc

Inventor： HSIEH HUNG-CHENG

IPC: G11C7/12 ,  G11C7/20 ,  G11C8/08 ,  G11C11/41 ,  G11C11/412

CPC classification number: G11C7/12 ,  G11C7/20 ,  G11C8/08 ,  G11C11/41 ,  G11C11/412

公开(公告)号：JPS62142416A

公开(公告)日：1987-06-25

申请号：JP21986086

申请日：1986-09-19

Applicant: XILINX INC

Inventor： HSIEH HUNG-CHENG

IPC: H03K3/3565 ,  H03K19/0185 ,  H03K19/0948

公开(公告)号：DE69132540D1

公开(公告)日：2001-04-05

申请号：DE69132540

申请日：1991-05-08

Applicant: XILINX INC

Inventor： HSIEH HUNG-CHENG ,  ERICKSON CHARLES R ,  CARTER WILLIAM S ,  CHEUNG EDMOND Y

IPC: G06F7/50 ,  G06F7/506 ,  G06F7/57 ,  G06F7/48

公开(公告)号：DE69132540T2

公开(公告)日：2001-07-05

申请号：DE69132540

申请日：1991-05-08

Applicant: XILINX INC

Inventor： HSIEH HUNG-CHENG ,  ERICKSON CHARLES R ,  CARTER WILLIAM S ,  CHEUNG EDMOND Y

IPC: G06F7/50 ,  G06F7/506 ,  G06F7/57 ,  G06F7/48

公开(公告)号：CA2037142A1

公开(公告)日：1991-11-11

申请号：CA2037142

申请日：1991-02-26

Applicant: XILINX INC

Inventor： HSIEH HUNG-CHENG ,  CARTER WILLIAM S ,  ERICKSON CHARLES R ,  CHEUNG EDMOND Y

IPC: G06F7/50 ,  G06F7/506 ,  G06F7/57

公开(公告)号：DE69031525D1

公开(公告)日：1997-11-06

申请号：DE69031525

申请日：1990-07-26

Applicant: XILINX INC

Inventor： FREEMAN ROSS H ,  HSIEH HUNG-CHENG

IPC: H03K19/173 ,  H03K19/177

Abstract: This invention provides additional circuitry for a configurable logic array having logic functions which are programmed by loading memory cells (C1,1,C1,2,...) which cause the logic array to generate a desired function. With the additional circuitry, the memory cells can also be used as memory for access by other parts of the logic array during operation.

公开(公告)号：DE69123274T2

公开(公告)日：1997-04-24

申请号：DE69123274

申请日：1991-03-27

Applicant: XILINX INC

Inventor： FREEMAN ROSS H ,  DUONG KHUE ,  HSIEH HUNG-CHENG ,  ERICKSON CHARLES R ,  CARTER WILLIAM S

IPC: G06F3/00 ,  H01L21/82 ,  H03K19/173 ,  H03K19/0175

公开(公告)号：DE3685804T2

公开(公告)日：1992-12-17

申请号：DE3685804

申请日：1986-09-18

Applicant: XILINX INC

Inventor： HSIEH HUNG-CHENG

IPC: H03K3/3565 ,  H03K19/0185 ,  H03K19/0948 ,  H03K19/094 ,  H03K19/003

公开(公告)号：CA2038162A1

公开(公告)日：1991-09-28

申请号：CA2038162

申请日：1991-03-13

Applicant: XILINX INC

Inventor： DUONG KHUE ,  HSIEH HUNG-CHENG ,  ERICKSON CHARLES R ,  CARTER WILLIAM S ,  FREEMAN ROSS H

IPC: G06F3/00 ,  H01L21/82 ,  H03K19/173

公开(公告)号：CA1267196A

公开(公告)日：1990-03-27

申请号：CA518485

申请日：1986-09-18

Applicant: XILINX INC

Inventor： HSIEH HUNG-CHENG

IPC: H03K3/3565 ,  H03K19/0185 ,  H03K19/0948 ,  H03K19/094 ,  H03K19/003

Abstract: TTL/CMOS COMPATIBLE INPUT BUFFER Hung-Cheng Hsieh A TTL/CMOS compatible input buffer includes an input inverter and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage to the source of the P-channel transistor in the inverter having a magnitude which forces the trigger point of the input inverter to assume a preselected value. Typically the preselected value is selected to be 1.4 volts in order to maximize the input noise margins. A second stage input inverter introduces hysterisis to improve the noise immunity of the system The reference voltage generator includes an operational amplifier connected to a voltage divider network. In the CMOS mode, the reference voltage generator is disabled and a voltage equal to power supply voltage is provided to the input inverter. As the result, the trigger point of input inverter is higher than 1.4 volts which provides a larger input noise margin. The voltage divider network and the operational amplifier are powered down so that no DC power is consumed.