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    Method for controlling laser beam power balance in laser scanning unit
    1.
    发明申请
    Method for controlling laser beam power balance in laser scanning unit 审中-公开
    激光扫描单元激光束功率平衡控制方法

    公开(公告)号：US20050083978A1

    公开(公告)日：2005-04-21

    申请号：US10963543

    申请日：2004-10-14

    Applicant: Yong-kwon Kim

    Inventor： Yong-kwon Kim

    IPC: B41J2/44 ,  G03G15/04 ,  G03G15/043 ,  H01S3/13 ,  H01S5/00 ,  H01S5/042 ,  H01S5/06 ,  H01S5/068 ,  H01S5/40 ,  H04N1/40 ,  H04N1/401

    CPC classification number: H04N1/40025 ,  H01S5/005 ,  H01S5/042 ,  H01S5/0617 ,  H01S5/06808 ,  H01S5/4031 ,  H04N1/4015

    Abstract: A method for controlling a laser beam power balance in a laser scanning unit is disclosed. The method of present invention comprises the steps of obtaining a first voltage value and a second voltage value corresponding to detection time points of a first laser beam and a second laser beam, respectively, emitted from the laser scanning unit. The first voltage value and the second voltage value are recorded in the laser scanning unit. After the laser scanning unit is mounted on a image forming apparatus, a third voltage value and a fourth voltage value are obtained corresponding to the detection time points of the first laser beam and the second laser beam, respectively, emitted from the laser scanning unit by driving the laser scanning unit mounted on the image forming apparatus. The third voltage value and the fourth voltage value are compared with the first voltage value and the second voltage value, respectively, thereby correcting the control voltage controlling the laser scanning unit by that variation.

    Abstract translation: 公开了一种用于控制激光扫描单元中的激光束功率平衡的方法。 本发明的方法包括以下步骤：分别获得与从激光扫描单元发射的第一激光束和第二激光束的检测时间点对应的第一电压值和第二电压值。 第一电压值和第二电压值被记录在激光扫描单元中。 在激光扫描单元安装在图像形成装置上之后，分别根据从激光扫描单元发射的第一激光束和第二激光束的检测时间点获得第三电压值和第四电压值， 驱动安装在图像形成装置上的激光扫描单元。 将第三电压值和第四电压值分别与第一电压值和第二电压值进行比较，从而通过该变化校正控制激光扫描单元的控制电压。

    INTEGRATED CIRCUIT DEVICE GATE STRUCTURES
    2.
    发明申请
    INTEGRATED CIRCUIT DEVICE GATE STRUCTURES 有权
    集成电路设计门结构

    公开(公告)号：US20090236655A1

    公开(公告)日：2009-09-24

    申请号：US12468414

    申请日：2009-05-19

    Applicant: Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

    Inventor： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

    IPC: H01L29/792

    CPC classification number: H01L21/28282 ,  B82Y10/00 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/792 ,  H01L29/7923

    Abstract: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

    Abstract translation: 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。 将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成电荷存储区，其中第一电介质层的电荷存储区域 在电荷存储区域下的隧道介电层。 金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。 包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。 还提供用于集成电路器件和存储单元的栅极结构。

    Fixing unit, image forming apparatus including the same, and method of controlling the fixing unit
    3.
    发明申请
    Fixing unit, image forming apparatus including the same, and method of controlling the fixing unit 审中-公开
    固定单元，包括该固定单元的图像形成设备以及控制定影单元的方法

    公开(公告)号：US20060099002A1

    公开(公告)日：2006-05-11

    申请号：US11168396

    申请日：2005-06-29

    Applicant: Yong-kwon Kim

    Inventor： Yong-kwon Kim

    IPC: G03G15/20 ,  G03G15/00

    CPC classification number: G03G15/2039

    Abstract: A fixing unit, an image forming apparatus including the same, and a method of controlling the fixing unit are provided. The fixing unit includes a heating element to apply heat to a printing medium to fix a transferred image thereon, a temperature sensor to sense temperature of the heating element, and a storage medium to store characteristic data of the heating element. The image forming apparatus includes the fixing unit and a controller to read the characteristic data of the heating element and to determine a control mode of the fixing unit based on the characteristic data of the heating element. The method of controlling the fixing unit includes accessing the fixing unit and reading the characteristic data of the heating element from the storage medium, and setting a control mode of the fixing unit based on the characteristic data of the heating element.

    Abstract translation: 提供了一种定影单元，包括该定影单元的图像形成设备以及一种控制定影单元的方法。 定影单元包括加热元件，用于向打印介质施加热量以固定其上转印的图像，温度传感器以感测加热元件的温度，以及存储介质以存储加热元件的特征数据。 图像形成装置包括定影单元和读取加热元件的特性数据的控制器，并且基于加热元件的特性数据确定定影单元的控制模式。 控制定影单元的方法包括访问定影单元并从存储介质读取加热元件的特征数据，并且基于加热元件的特征数据设置定影单元的控制模式。

    Integrated circuit device gate structures
    4.
    发明授权
    Integrated circuit device gate structures 有权
    集成电路器件门结构

    公开(公告)号：US07964907B2

    公开(公告)日：2011-06-21

    申请号：US12468414

    申请日：2009-05-19

    Applicant: Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

    Inventor： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

    IPC: H01L21/00

    CPC classification number: H01L21/28282 ,  B82Y10/00 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/792 ,  H01L29/7923

    Abstract: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

    Abstract translation: 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。 将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成电荷存储区，其中第一电介质层的电荷存储区域 在电荷存储区域下的隧道介电层。 金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。 包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。 还提供用于集成电路器件和存储单元的栅极结构。

    Methods of forming integrated circuit device gate structures
    6.
    发明授权
    Methods of forming integrated circuit device gate structures 有权
    形成集成电路器件门结构的方法

    公开(公告)号：US07550347B2

    公开(公告)日：2009-06-23

    申请号：US11510059

    申请日：2006-08-25

    Applicant: Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

    Inventor： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

    IPC: H01L21/00

    CPC classification number: H01L21/28282 ,  B82Y10/00 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/792 ,  H01L29/7923

    Abstract: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

    Abstract translation: 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。 将元素周期表第4组的选定元素的离子注入到第一电介质层中，以在第一电介质层中形成具有小于约0.5厘米每秒（cm 2 / s）的热扩散率的离子，从而在第一电介质层中形成电荷存储区， 在电荷存储区域下的隧道介电层。 金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。 包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。 还提供用于集成电路器件和存储单元的栅极结构。

    Integrated circuit device gate structures and methods of forming the same
    7.
    发明申请
    Integrated circuit device gate structures and methods of forming the same 有权
    集成电路器件栅极结构及其形成方法

    公开(公告)号：US20070128846A1

    公开(公告)日：2007-06-07

    申请号：US11510059

    申请日：2006-08-25

    Applicant: Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

    Inventor： Sam-jong Choi ,  Yong-kwon Kim ,  Kyoo-chul Cho ,  Kyung-soo Kim ,  Jae-ryong Jung ,  Tae-soo Kang ,  Sang-Sig Kim

    IPC: H01L21/4763

    CPC classification number: H01L21/28282 ,  B82Y10/00 ,  H01L29/42324 ,  H01L29/42332 ,  H01L29/792 ,  H01L29/7923

    Abstract: Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm2/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

    Abstract translation: 形成用于集成电路存储器件的栅极结构的方法包括在集成电路衬底上形成具有低于7的介电常数的第一介电层。 将元素周期表第4组的选定元素的离子注入到第一介电层中，并且具有小于约0.5厘米每秒（cm 2 / s）的热扩散率，从而形成电荷存储 区域，在电荷存储区域下方具有隧道介电层。 金属氧化物第二电介质层形成在第一电介质层，第二电介质层上。 包括第一和第二电介质层的衬底被热处理以在电荷存储区域中形成多个离散的电荷存储纳米晶体，并且在第二电介质层上形成栅极电极层。 还提供用于集成电路器件和存储单元的栅极结构。

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