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公开(公告)号:EP3202031A4
公开(公告)日:2018-06-20
申请号:EP15847592
申请日:2015-10-03
Applicant: ZARETSKY HOWARD
Inventor: BABAIE MASOUD , STASZEWSKI ROBERT BOGDAN
CPC classification number: H03B5/1212 , H03B5/1215 , H03B5/1218 , H03B5/1228 , H03B5/124 , H03B5/1265 , H03B5/1281 , H03B5/1293 , H03B5/1296 , H03J2200/10 , H03L7/081 , H03L7/0991 , H03L7/1976
Abstract: A novel and useful RF oscillator suitable for use in applications requiring ultra-low voltage and power. The oscillator structure, employing alternating current source transistors, combines the benefits of low supply voltage operation of conventional NMOS cross-coupled oscillators together with high current efficiency of the complementary push-pull oscillators. In addition, the 1/f noise upconversion is also reduced. The oscillator can be incorporated within a wide range of circuit applications, including for example a conventional phase locked loop (PLL), all-digital phase-locked loop (ADPLL), wireline transceiver circuits and mobile devices.
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公开(公告)号:EP3219017A4
公开(公告)日:2018-06-13
申请号:EP15847809
申请日:2015-10-03
Applicant: ZARETSKY HOWARD
Inventor: BABAIE MASOUD , STASZEWSKI ROBERT BOGDAN
IPC: H03H7/38 , H03F1/02 , H03F1/56 , H03F3/193 , H03F3/21 , H03F3/217 , H03F3/24 , H03F5/00 , H03H7/09 , H03H7/42 , H04B1/06
CPC classification number: H03H7/38 , H01F27/2823 , H01F27/29 , H01Q1/50 , H03F1/0205 , H03F1/565 , H03F3/193 , H03F3/211 , H03F3/2171 , H03F3/2176 , H03F3/245 , H03F2200/318 , H03F2200/451 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2203/21106 , H03F2203/21139 , H03H7/40
Abstract: A novel and useful transmitter (TX) architecture for ultra-low power (ULP) radios. An all-digital PLL employs a digitally controlled oscillator (DCO) having switching current sources to reduce supply voltage and power consumption without sacrificing phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL after settling to reduce its sampling rate or shut it off entirely during direct DCO data modulation. A switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter has been realized in 28 nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5 mW while delivering 0 dBm/3 dBm RF power in Bluetooth Low-Energy.
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公开(公告)号:WO2016054617A3
公开(公告)日:2016-05-26
申请号:PCT/US2015053898
申请日:2015-10-03
Applicant: ZARETSKY HOWARD
Inventor: BABAIE MASOUD , STASZEWSKI ROBERT BOGDAN
CPC classification number: H03H7/38 , H01F27/2823 , H01F27/29 , H01Q1/50 , H03F1/0205 , H03F1/565 , H03F3/193 , H03F3/211 , H03F3/2171 , H03F3/2176 , H03F3/245 , H03F2200/318 , H03F2200/451 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2203/21106 , H03F2203/21139 , H03H7/40
Abstract: A novel and useful transmitter (TX) architecture for ultra-low power (ULP) radios. An all-digital PLL employs a digitally controlled oscillator (DCO) having switching current sources to reduce supply voltage and power consumption without sacrificing phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL after settling to reduce its sampling rate or shut it off entirely during direct DCO data modulation. A switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter has been realized in 28nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6mW/5.5mW while delivering 0dBm/3dBm RF power in Bluetooth Low-Energy.
Abstract translation: 一种用于超低功耗(ULP)无线电的新颖有用的发射机(TX)架构。 全数字PLL采用具有开关电流源的数字控制振荡器(DCO),以降低电源电压和功耗,而不会牺牲相位噪声和启动裕度。 它还降低了1 / f噪声,允许ADPLL在稳定后降低采样率或在直接DCO数据调制期间完全关闭它。 开关功率放大器在E / F2类中工作时集成了其匹配网络,以最大限度地提高其效率。 发射机已经在28nm CMOS中实现,并且满足所有金属密度和其他制造规则。 它在蓝牙低功耗中提供0dBm / 3dBm射频功率,消耗3.6mW / 5.5mW。
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