Abstract:
Aparato de circuito de enganche de fase para generar una señal oscilatoria enganchada en fase a un componente de una señal adicional, comprende un oscilador variable para generar la señal oscilatoria y una fuente de la señal adicional. Un detector de fase que responde a la señal oscilatoria y al componente de la señal adicional, proporciona una señal de error de fase que está apropiada al oscilador variable vía un limitador. Se proporcionan medios de circuito para controlar el nivel de limitacion del limitador. La limitacion dual mejora substancialmente la tolerancia de ruido del circuito y reduce la sensibilidad del circuito a inversiones de fase ocasionales del componente de la señal adicional. Se proporcionan mejoramientos adicional a estabilidad de circuito e inmunidad de ruido mediante un detector de desenganche, que detecta y totaliza las rotaciones de fase en una área seleccionada de un plano de fase y mediante un detector de envolvente de fase que mantiene una indicacion de cierre durante el ángulo de fase.
Abstract:
An oscillator provided with an amplitude controller (AMPREG1) which is coupled by an input (G1) to an amplitude reference terminal (AMPREF1). The amplitude of the oscillator signal at the output terminal (KU) can be adjusted through coupling of a voltage-generating means to the amplitude reference terminal (AMPREF1).
Abstract:
A ring-type oscillator with a plurality of delay cells (10, 12, 14, 16) including differential pairs of MOS transistors (MN5, MN6; MN8, MN9; MN11, MN12; MN14, MN15). Current sources (MN4, MN7, MN10, MN13) supply current to each pair, and the magnitude of the current supplied is variable by a control voltage to alter the delay of the MOS devices, thereby to alter the frequency of oscillation. Each delay cell MOS device is connected in series with another MOS device (MP4-MP11) biased into its linear region to act as a load resistance. This load is variable by the control voltage so as to tend to maintain the gain of the delay cells constant with changes in frequency of oscillation.
Abstract:
An electronic circuit uses a resonance technique to reduce power consumption. The circuit contains function circuitry (14) that performs electronic functions. Certain elements (14F) of the function circuitry change state at a circuit frequency in response to one or more input signals, typically clock signals (CKR and C &cir& NOt K &cir& NOt R &cir& NOt ), that change state at the circuit frequency. A resonant system (50 or 140), which oscillates at the circuit frequency, is operated close to a resonant frequency so that the resonant system is largely in resonance. The resonant system is coupled to the function circuitry in order to help the indicated elements in changing state by overcoming parasitic capacitances and/or inductances associated with the function circuitry.
Abstract:
A topology for a high speed voltage controlled oscillator (VCO) with quadrature outputs is produced utilizing four inverting differential circuits (12, 14, 16, 18). The fully differential four stage ring oscillator has outputs from alternate delay circuits combined in balanced exclusive OR gate frequency doublers (24, 26) to provide both in-phase and quadrature output signals at twice the ring oscillator frequency. The period of the quadrature delay signals is four gate delays and is easily realized in the Ghz frequency ranges. The in-phase and quadrature output signals are again combined in a balanced exclusive OR gate frequency doubler (36) to obtain a final output frequency quadruple the ring oscillator frequency.
Abstract:
A voltage controlled oscillator (900) is formed of two differential transconductance stages (902-1, 902-2) which have negative output conductances. The first stage (902-1) has a positive output coupled to a positive input of the second stage (902-2), and a negative output coupled to a negative input of the second stage. The second stage (902-2) has a positive output coupled to a negative input of the first stage (902-1), and a negative output coupled to a positive input of the first stage.
Abstract:
A timing generator contains an oscillator section (10) formed with a plural number of stages (S1-SN) for respectively producing a like number of stage signals (VS1-VSN) that sequentially change signal values at a basic oscillator frequency (f0). The oscillator section is typically implemented as a ring oscillator. In response to the stage signals, a timing-signal generating section (14) generates one or more timing signals (VT1-VTM), each having at least two transitions corresponding to transitions of two or more of the stage signals. A control section (12), preferably arranged in a phase-locked loop; causes the oscillator frequency and a reference frequency (fR) to have a substantially fixed relationship.