公开(公告)号：EP0102600A3

公开(公告)日：1986-11-26

申请号：EP83108437

申请日：1983-08-26

Applicant: HITACHI, LTD. ,  HITACHI VIDEO ENGINEERING, INC.

Inventor： Shibata, Akira ,  Ohashi, Shinichi

IPC: G11B05/008 ,  G11B15/467 ,  G11B20/00 ,  G11B15/18 ,  G11B05/09

CPC classification number: G11B5/09 ,  G11B5/0086 ,  G11B15/4675 ,  G11B20/00007 ,  G11B20/10527 ,  G11B27/032 ,  G11B27/036 ,  G11B2220/90 ,  H04N5/928 ,  H04N9/802

Abstract: A helical scan type magnetic tape recording/reproducing apparatus for recording/reproducing information, for example, a large amount of time-compressed audio PCM signals on a plurality of information tracks disposed in parallel to the direction of the tape running. Each of the time-compressed audio PCM signals are recorded with one of four frequencies of a pilot signal on a selected information track, and each of the time-compressed audio PCM signals recorded on the information tracks can be selectively reproduced from the corresponding information track. The apparatus includes a circuit for generating a plurality of track indicating pulses which respectively correspond to the information tracks and are phase-locked to the rotation of the rotating heads, and a circuit for selecting one of the track indicating pulses, which is supplied to control time compressing/expanding of an audio signal.

公开(公告)号：EP0098153A3

公开(公告)日：1986-10-01

申请号：EP83303732

申请日：1983-06-28

Applicant: NIPPON TELEGRAPH AND TELEPHONE CORPORATION ,  FUJITSU LIMITED

Inventor： Kuroda, Hideo ,  Honma, Toshihiro ,  Mukawa, Naoki ,  Fukuda, Hiroshi ,  Matsuda, Kiichi

IPC: G11B05/09 ,  H04L25/49 ,  H03M07/40 ,  G11B20/10 ,  H04N01/419

CPC classification number: G11B20/1426 ,  G11B20/10527 ,  H03M7/42

Abstract: @ A digital data code conversion circuit for a variable-word-length data code comprises a data code conversion portion (4) and a preparation circuit (3) wherein a variable-word-length data code having a word length greater than a number of n bits is divided into a plurality of variable-word-length data codes having a word length less than or equal to the number of n bits in the preparation circuit (3) and the divided variable-word-length data codes are converted into fixed-ward-length data codes having a word length n in the data code conversion portion (4).

公开(公告)号：EP0119445A3

公开(公告)日：1985-12-04

申请号：EP84101376

申请日：1984-02-10

Applicant: PRIME COMPUTER, INC.

Inventor： Long, Charles Comey ,  Lounsbury, David Morgan ,  Curtin, Richard Roy

IPC: G11B05/09 ,  H04L25/49

CPC classification number: G11B20/1419

Abstract: Apparatus is disclosed for reading phase encoded digital data from a nine-track magnetic tape which apparatus includes timing circuitry for deriving a clock signal from the recorded data. A portion of the timing circuitry is associated with each track on the tape and automatically accomodates, without generating errors, phase changes in the derived clock signal in that track caused by speed variations in the magnetic tape transport and due to bit shifts caused by certain data patterns. Tape transport speed variations are sensed and the derived clock rate is corrected by a digital phase-locked loop which uses a counter that is clocked at a constant rate to determine the timing "window" during which the circuitry looks for signal transitions on the magnetic tape. A running average of the count remaining in the counter at the time when a transition actually occurs is used to adjust the counter starting value until equilibrium is established. The circuitry accomodates clock signal phase changes caused by bit shifting by calculating an expected arrival time for a data transition and varying the width of the timing window depending on whether the data transition is received either prior to or subsequent to the expected arrival time.

公开(公告)号：EP0093200A3

公开(公告)日：1985-08-14

申请号：EP82111445

申请日：1982-12-10

Applicant: International Business Machines Corporation

Inventor： Klaassen, Klaas B.

IPC: G11B05/09 ,  G11B05/58 ,  G11B05/47

CPC classification number: G11B5/5965 ,  G11B5/02 ,  G11B5/03

Abstract: A method for recording high frequency signals representing data with simultaneous readout of low frequency information, such as servo information prerecorded on a magnetic disk (22), comprises the step of modulating (12) with the data (14) a carrier signal (10) having a repetition frequency displaced significantly from the baseband of the data. The nonlinearity of the recording channel shifts the modulated signal spectrum into the low frequency baseband so that the data is magnetically recorded while the low frequency prerecorded information is read out.

公开(公告)号：EP0085517A3

公开(公告)日：1985-06-26

申请号：EP83300318

申请日：1983-01-21

Applicant: SONY CORPORATION

Inventor： Odaka, Kentaro Patent Division

IPC: G11B05/09 ,  G11B15/14

CPC classification number: G11B20/00007 ,  G11B5/0086 ,  G11B5/09 ,  G11B15/14 ,  G11B20/1803 ,  G11B20/1806 ,  G11B20/1813 ,  H04N5/928

Abstract: In apparatus for recording and/or reproducing digital signals wherein there is a data blank interval (τ) which is a buffer interval during which rotary heads change over or for a junction or splice between data, and wherein time base compression is effected, redundant data for error detection or error corection is recorded during the data blank interval (τ) before and after a data transmitting interval.

公开(公告)号：EP0073330A3

公开(公告)日：1984-05-16

申请号：EP82106400

申请日：1982-07-16

Applicant: International Business Machines Corporation

Inventor： Nolta, Arthur Herbert

IPC: G11B05/09 ,  G11C09/06 ,  G06F13/00

CPC classification number: G11C29/70 ,  G11B20/1883 ,  G11B2220/20

Abstract: Data associated with a defective area (18) of a backing store (13) and stored in an alternate area (25), such as defective and alternate tracks in a direct access storage device, is pinned to a high speed buffer front store (14) based upon usage for such data. A first replacement control governs buffer operation for data from good areas of the backing store and a second independent replacement control governs buffer operation for data from alternate storage areas. Limitations are imposed on the amount of data subject to the second replacement control.

公开(公告)号：EP0091215A3

公开(公告)日：1983-11-30

申请号：EP83301340

申请日：1983-03-10

Applicant: AMPEX CORPORATION

Inventor： Chan, Steven S.

IPC: G11B05/09

CPC classification number: G01R29/027 ,  G11B20/1423 ,  H03K9/08

Abstract: To decode a binary signal without regard to the speed at which it is read, each transition in the binary signal is detected, and the time lapse between successive transitions is detemined to thereby establish the length of a pulse in the binary signal. The length of one pulse is compared with that of the immediately preceding bit cell to determine whether their lengths are approximately the same or vary by a factor of approximately 2, and any change in the binary state of the signal is determined accordingly. A multiplexing technique is employed to simultaneously decode a number of signals in this manner.

公开(公告)号：EP0052432A3

公开(公告)日：1982-12-08

申请号：EP81304903

申请日：1981-10-20

Applicant: SONY CORPORATION

Inventor： Ive, John Goodwin Spencer ,  Thirlwall, Alan Clive

IPC: G11B05/09 ,  H04N05/93

CPC classification number: H04L7/08 ,  G11B20/10 ,  G11B20/12 ,  G11B20/1806 ,  G11B27/3027 ,  G11B2220/90 ,  H04N5/935

Abstract: Apparatus for extracting synchronizing information from an incoming serial-bit digital television signal formed of a sequence of word blocks, each word block being formed of N n-bit words and each word block including a predetermined serial group of m bits forming said synchronizing information, and for de-serializing the incoming digital signal in dependence on the synchronizing information, comprises an m-stage shift register (2) through which the incoming digital signal is stepped at the bit rate of the incoming digital signal, the first shift register (2) supplying a pulse when it holds the predetermined serial group of m bits, a frequency divider (9) to derive from the incoming digital signal a word rate clock pulse signal, an n-stage shift register (4) through which each said pulse is stepped at the bit rate of the incoming digital signal, a latch circuit (10) synchronized with the word rate clock pulse signal to derive n-bit phase words the bits of which correspond respectively to the conditions of the n stages of the shift register (4), comparators (16 to 19) comparing each phase word with at least one other phase word derived N or an integral multiple of N word periods of the incoming digital signal earlier, the comparators (16 to 19) supplying a control signal only when at least one of the comparisons indicates two phase words which are identical and both contain a bit corresponding to a said pulse, the position of this bit in the phase words indicating the phasing of the word rate clock pulse signal relative to the words of the incoming digital signal, and circuits (5,6,7,24) to de-serialize the incoming digital signal into parallel-bit n-bit words under control of the control signal.

公开(公告)号：EP0118121A3

公开(公告)日：1988-07-27

申请号：EP84102240

申请日：1984-03-02

Applicant: Research Corporation

Inventor： Titchener, Mark Renfreu

IPC: H04L07/04 ,  G11B05/09 ,  H03M07/42

CPC classification number: G11B20/1426 ,  H04L7/04

Abstract: The specification discloses a method and apparatus for' encoding and decoding a variable length augmented code for use in the transmission of sequential information as an indefinite length string of data. Both binary and alternate character code sets are discussed for transmitting and translating information. The variable length code symbols are self synchronizing, and will automatically reestablish synchronization within two characters if a bit or number of bits is lost through noise or faulty transmission. The resynchronization is automatic and occurs by virtue of the construction of the variable length augmented codes. In addition, a method and means of creating a fixed length depleted code for use in digital processors and digital storage media is also disclosed. Inasmuch as most digital processors utilize fixed length words, it is desirable to be able to convert the variable length augmented code into a fixed length depleted code, and to be able to reconvert from the depleted code back to the augmented code without necessity of resorting to an extensive lookup table for each of the characters. In creating the augmented set of self synchronizing variable length code symbols, the original character set C° is augmented 9 times until the C q = 2 q (n-1) +1 wherein n represents the number of distinct elements in the original character set C° that was augmented, and C q is equal to the number of symbols derived in the final augmented set C q , and is equal to or greater than the desired number of characters to be used in the data handling and communication.

公开(公告)号：EP0117756A3

公开(公告)日：1987-08-19

申请号：EP84301277

申请日：1984-02-27

Applicant: NEC CORPORATION

Inventor： Kaneko, Takashi

IPC: G11B05/09 ,  G06F11/10 ,  H04L01/10

CPC classification number: G11B20/1876

Abstract: The circuit (21) implements a known interpolation algorithm processing words flagged (F n , F n+1 ) as in error or correct. A correct word is passed on unchanged. An incorrect word is replaced by the means of the most recent correct word and the ensuing word, if that be correct, whereas it is replaced by the most recent correct word if the ensuing word is also incorrect. In order to avoid the complexity of known circuits with multiple latches and a complex output multiplexer, the words are written selectively into two address locations (a, β) in a RAM 15 in such a way that an adder 16 is always able to furnish the desired result to an output latch (17).