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公开(公告)号：EP0118954A3
公开(公告)日：1988-06-22
申请号：EP84200318
申请日：1984-03-06
Applicant: International Business Machines Corporation
Inventor： Aiken, John Andrew, Jr.
CPC classification number: G06F17/30955 , G06F3/0601 , G06F2003/0697
Abstract: In a word processing system 10 storing a text stream on a direct access storage device (DASD) for recall and editing, the text stream is organized into a document, which is stored on the DASD 22 as a data set. The data setconsists of an index portion and a portion containing text records. The index portion is divided into nodes, of which the primary node is called the root node. A volume 500 which refers to the full contents of the DASD can be formatted to contain multiple zones 502-508, each of which is logically independent of all other zones, when the contents of a storage volume can be divided conceptually into portions the uses of which are logically independent. Each zone has its own media allocation map, and data sets 510-522 whose root is allocated within a given zone have all allocations within that same zone. If more than one data set with a given data set type exists on the storage volume, all of those data sets 511, 513, 516 and the data set directory 520 for that data set type are allocated within a single zone 504. For each zone, a recovery required indicator 325 is provided so that zones not requiring recovery need not be scanned when volume recovery is being performed. When only one zone is being recoverd, the logical sector number of the root node referenced by the index element in the anchor is used to determine whether or not that data set lies in the zone being recovered, and to skip data sets that do not lie in the zone (675-691).
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2.发明公开
公开(公告)号：EP0123322A3
公开(公告)日：1987-09-09
申请号：EP84104700
申请日：1984-04-26
Applicant: NEC CORPORATION
Inventor： Tomimitsu, Yasuharu
CPC classification number: G11B20/1809 , G11B20/12
Abstract: in an address indication circuit for use in indicating memory addresses of a random access memory to provide delays necessary for successive channels, channel addresses are determined relative to the memory addresses by assigning a reference number to a leading one of the channels and by successively accumulating the reference number and numbers determined for the delays to decide results of accumulation as the remaining channel addresses. The respective channel addresses are stored in a read-only memory (80) and added by an adder (83) to a base address variable at every time interval to provide memory addresses. When the memory addresses are equal in number to a preselected number, the base address may be produced by a counter (81) carrying out operation between zero and the preselected number less one. The adder adds the reference number to the base address modulo the preselected number.
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公开(公告)号：EP0114938A3
公开(公告)日：1987-02-25
申请号：EP83110505
申请日：1983-10-21
Applicant: International Business Machines Corporation
Inventor： Patel, Arvind Motibhai
CPC classification number: H03M13/151 , G11B5/09 , H03M13/1545 , H03M13/1585
Abstract: In the multibyte error correcting system, up to t errors are correctable by processing 2t syndrome bytes. Syndrome bytes are converted into t+1 coefficients of the error locator polynomial by predetermined product operations and exclusive-OR operations involving selected syndrome bytes to produce cofactors that correspond to the desired coefficients when less then t errors occurred in the codeword. The cofactors are combined to produce coefficients when t errors occur and the correct set of coefficients are selected in accordance with the number of errors that are detected. Up to t erroneous bytes in one codeword and corrected during its transfer from the system while the next codeword is entered in the system, so that correction is on-the-fly.
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公开(公告)号：EP0109551A3
公开(公告)日：1986-12-03
申请号：EP83110417
申请日：1983-10-19
Applicant: THE STYPHER CORPORATION
Inventor： Moxon, Edwin C.
CPC classification number: G11B20/1813 , G11B27/3054 , G11B2220/90
Abstract: Apparatus for decoding digitally-coded address signals embedded in video signals recorded on magnetic tape is disclosed. The apparatus can properly decode the address signals at both slow and fast tape speeds and utilizes a variable-frequency oscillator to generate timing signals for decoding the digitally-coded address. The address signals encoded on the magnetic tape normally include an error code which can be detected by conventional error checking circuitry and used to check whether the address signals have been correctly received. The oscillator frequency is adjusted in accordance with an error signal generated by the error checking circuitry until error-free detection of the address signals is achieved.
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公开(公告)号：EP0129849A3
公开(公告)日：1986-04-09
申请号：EP84107110
申请日：1984-06-20
Applicant: HITACHI, LTD.
Inventor： Okamoto, Hiroo , Kobayashi, Masaharu Hitachi-Hachimanyama , Nishimura, Keizo , Noguchi, Takaharu , Arai, Takao , Shibuya, Toshifumi
IPC: G11B05/09
CPC classification number: G11B20/1809
Abstract: This invention relates to an error correction upon reproduction of digital signals. The error correction is performed by decoding code words such as cross-interleaved Reed Solomon codes, in which first code blocks are formed by a plurality of information words which are in the first arrangement state and a plurality of first check words which are produced by codes associated with the plurality of information words with a Hamming distance of d,, and second code blocks are formed by a plurality of information words and a plurality of first check words which are in the second arrangement state and which consist of the said plurality of information words and the said plurality of first check words which are respectively included in the different first code blocks, and by a plurality of second check words which are produced by codes associated with the plurality of information words and the plurality of first check words with a Hamming distance of d 2 . At the first decoding stage, at least errors are detected and at the same time the flags indicative of the decoding states are i added with respect to the second code blocks. At the second decoding stage, in accordance with the contents of the flags and on the basis of a combination of p 2 and q selected from their combinations satisfying 2p 2 +q≤d 1 -1, errors are detected and errors of p 2 words are corrected and erasures of q words to which the flags were added are corrected with respect to the first code blocks.
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Patent Agency Ranking
公开(公告)号：EP0094293A3
公开(公告)日：1985-09-18
申请号：EP83400869
申请日：1983-04-29
Applicant: DIGITAL EQUIPMENT CORPORATION
Inventor： Rub, Bernardo , Weng, Lih J.
CPC classification number: G11B20/1426
Abstract: The present invention provides translation circuitry, which in one mode of operation acts to encode variable length data words into fixed rate data coded words for use with a communication channel, or a recording means, such as a magnetic recording medium and which in another mode of operation acts to decode the coded words to data words. The translation circuitry functions such that in an encoding operation, the second and third bits of a three-bit coded word, respectively, have the same binary values as the first and second bits of the data word, which the coded word represents and the second and sixth bits of a six-bit coded word, respectively, have the same binary values as the third and fourth bits of the data word which the coded word represents.
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公开(公告)号：EP0086658A3
公开(公告)日：1984-07-25
申请号：EP83300741
申请日：1983-02-15
Applicant: SONY CORPORATION
CPC classification number: G11B20/1204 , G11B20/1202 , G11B20/18 , G11B20/1813 , G11B20/225 , G11B27/10 , G11B2220/90
Abstract: A time base correcting apparatus is capable of correcting time base erros contained in a digital signal supplied thereto in the form of successive data blocks each data block including a plurality of data words and a block address which cycles with a predetermined phase relation relative to a certain reference signal. A memory (16) is provided, having a plurality of addressable storage locations, each arranged to store a respective data block. A write-in address (21) to identify the particular storage locations is generated according to data block addresses and read-out addresses. The write-in address (21) is varied (29) by a lock phase mode signal (5) indicative of a phase relation at which an incoming digital signal is locked to a reference signal, so that notwithstanding the phase mode in which the digital signal is locked to the reference signal, the correction ability of the time base correcting apparatus can be prevented from being lowered.
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公开(公告)号：EP0053505A3
公开(公告)日：1983-07-06
申请号：EP81305641
申请日：1981-11-27
Applicant: SONY CORPORATION , KABUSHIKI KAISHA TOSHIBA
Inventor： Hoshimi, Susumu , Kojima, Tadashi
CPC classification number: G11B20/1809
Abstract: A PCM signal processing apparatus is arranged to receive successive transmission blocks, each of which comprise time-interleaved PCM data, error correction and error detection words. The apparatus has an error detector (16) responsive to the error detection words for detecting errors in a received transmission block and error identifying means (18, 22, 23) for identifying errors in each of the time-interleaved words included in the received transmission block which has been detected. A de-interleaver (17) is provided for time-deinterleaving each received transmission block to recover a de-interleaved block comprising de-interleaved PCM and error correction words, with errors in the de-interleaved words being respectively identified. A syndrome generating device (18) is coupled to the de-interleaver (17) for generating error syndromes using the de-interleaved PCM and error correction words in the de-interleaved block. An error correcting device (20) responsive to the error syndromes corrects erroneous PCM words in the de-interleaved block as a function of the remaining error free PCM and the error correction words in the de-interleaved block. An error compensating device (21) is responsive to the identification of errors by the error identifying device and compensates the erroneous PCM words in the de-interleaved block with a substitute PCM word when error correction by the error correcting device (20) is impossible. An inhibit device (24) inhibits the error correcting device (20) when all of the error detection words in the de-interleaved block are identified as erroneous and it discontinues inhibiting when the relationship between the identification by the error identifying device and the error syndrome indicates that no error exists.
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公开(公告)号：EP0037260A3
公开(公告)日：1982-04-21
申请号：EP81301313
申请日：1981-03-26
Applicant: VICTOR COMPANY OF JAPAN, LIMITED
Inventor： Ito, Yasuo
CPC classification number: G11B20/10009 , H04L7/033 , H04L25/242
Abstract: A data regenerative system adapted to receive data signals transmitted with the Non-Return-to-Zero mode comprises a comparator (10) for comparing the voltage level of the received data with a variable threshold to generate a digital comparator output. D-type flip-flops (DFF1, DFF2) are arranged to receive the comparator output to generate first and second pulses respectively in response to a data strobe clock pulse. The time difference between the first and second pulses is detected by a first subtractor (21, 22, 23) to generate an error voltage which is applied to the comparator (10) as its threshold to keep the crossing points of the eye pattern of the received signal aligned on the threshold level. A variable width monostable multivibrator (MM) is responsive to synchronization pulses to generate the data strobe clock pulses with a duration that is a function of an output of a second subtractor (26, 27, 28) representing the difference between each period of the first and second pulses and one-half period of a third pulse generated by a D-type flip-flop (DFF4) in response to the leading edge transition of the output of the monostable multivibrator (MM) in the presence of the first and second pulses. Output pulses are regenerated in response to the output of the monostable multivibrator in the presence of the comparator output.
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公开(公告)号：EP0216329A3
公开(公告)日：1988-10-05
申请号：EP86112962
申请日：1986-09-19
Applicant: Deutsche Thomson-Brandt GmbH
Inventor： Scholz, Werner, Dipl.-Ing.
CPC classification number: H04L7/06 , G11B20/10527 , G11B20/12 , G11B27/3027 , G11B2220/90 , G11B2220/913 , H04L7/033 , H04L7/041 , H04L7/046
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