公开(公告)号：EP0117287A3

公开(公告)日：1987-02-25

申请号：EP83111128

申请日：1983-11-08

Applicant: International Business Machines Corporation

Inventor： Patel, Arvind Motibhai

IPC: G11B05/09 ,  G06F11/10 ,  H04L01/10

CPC classification number: G11B20/1809 ,  H03M13/15

Abstract: A two-level multibyte error correcting system for correcting up to t, one-byte errors in a codeword in response to processing 2t, non-zero syndrome bytes at the first level and up to t 2 one-byte errors in a codeword in response to processing 2t 2 non-zero syndrome bytes at the second level when processing said 2t, syndrome bytes at said first level does not produce an all zero pattern for said 2t 2 syndrome bytes. The system is particularly applicable to data handling devices such as disk files, where in a relatively long block of data may be divided into subblocks, each of which may contain up to t, - x one-byte errors that are correctable at the first level by processing 2t, non-zero syndrome bytes. One identifiable subblock of the word may contain up to t, + x one-byte errors which are correctable by processing said 2t 2 non-zero syndrome bytes where 0 ≤ x 2 - t 1 ).

公开(公告)号：EP0112988A3

公开(公告)日：1987-02-04

申请号：EP83110500

申请日：1983-10-21

Applicant: International Business Machines Corporation

Inventor： Patel, Arvind Motibhai

IPC: G06F11/10 ,  G11B05/09 ,  H04L01/10

CPC classification number: H03M13/151 ,  G11B20/1833

Abstract: A syndrome processing unit for a multibyte error correcting system includes logical circuitry for performing product operation on selected pairs of 8-bit syndrome bytes, and exclusive-OR operations on selected results of the product operations are selectively combined to define usable cofactors that correspond to coefficients of the error locator polynomial if the codeword contains less than the maximum number of errors for which the system has been designed.

公开(公告)号：EP0117753A3

公开(公告)日：1986-12-17

申请号：EP84301270

申请日：1984-02-27

Applicant: SONY CORPORATION

Inventor： Omori, Takashi c/o Patent Division ,  Sugiki, Hiraku c/o Patent Division

IPC: G11B05/58 ,  G11B05/09 ,  G11B15/46

CPC classification number: G11B15/4677 ,  G11B5/588 ,  G11B5/5921

Abstract: In a system for recording and reproducing digital signals on a magnetic tape (12) using a rotary head (11 A, 11 B), in which the signals are recorded as a series of slanted tracks (14A, 14B) without guard bands between adjacent tracks (14A, 14B), a pilot signal that was recorded during the recording process is used to control the tracking of the playback head (11 A, 11 B). The pilot signal is recorded at a specific position in a specific pilot signal record region, independent from the region of the track (14A, 14B) at which the information signal is recorded, and the pilot signal is arranged at a predetermined position or positions being a specified distance from an end of each track (14A, 14B) in its longitudinal direction, and only alternate tracks receive the pilot signal. When the recorded tracks (14A, 14B) are reproduced by a rotary playback (11 A, 11 B) having a tracing width that is greater than the width of the track (14A, 14B), the pilot signals from the adjacent tracks (14A, 14B) will be detected and can be compared in level, with the comparison output being used to control the tracking of the rotary playback head (11 A, 11 B).

公开(公告)号：EP0109248A3

公开(公告)日：1986-08-13

申请号：EP83306794

申请日：1983-11-08

Applicant: FUJITSU LIMITED

Inventor： Uno, Hiroshi

IPC: G11B05/09 ,  G11B20/10

CPC classification number: G11B20/10194 ,  G11B20/10212

Abstract: 57 A write data compensating circuit in a magnetic recorder comprises a shifting circuit (40) for shifting binary data (Din) in time relation and for producing front, present, and rear signals related to the binary data, and a combination logic circuit (50) for applying a preshift to the present signal provided as write data in accordance with a pattern of the front, present, and rear signals. The combination logic circuit comprises a first circuit (51-55) which is operative to detect the pitch of each two adjacent inversions of magnetization to be created by the write data, and a second circuit (58-63) operative to adjust each pulse width of the write data on the basis of an analysis by the first circuit.

公开(公告)号：EP0094671A3

公开(公告)日：1986-07-16

申请号：EP83104820

申请日：1983-05-16

Applicant: SONY CORPORATION

Inventor： Odaka, Kentaro ,  Sako, Yoichiro ,  Kojima, Yuichi ,  Nakano, Kenji ,  Moriwaki, Hisayoshi

IPC: G11B05/09 ,  H04L01/10 ,  G06F11/10

CPC classification number: G11B20/1809

Abstract: In the recording/reproducing of digital audio signals, errors are detected and corrected by using two parity words, one arranged at the center of the block formed of data words and the arranged at one end of the block. The probability that uncorrectable error will be present in the center of the block is relatively high, so placing the parity word there prevents loss of the more valuable data. Maximum correctable burst errors are determined by the length of the block, so placing the other parity word on the end of the block lengthens it and improves burst error correction. The parity words are arranged as indicated before adding a cyclic redundancy check (CRC) code to the data signal and then modulation coding the signal before recording. During playback, the reproduced signal is demodulated and the CRC code used to detect errors for which error pointers are generated. The reproduced data is read into memories (3,4) in accordance with generated addresses and the pointers prevent the writing in of words found to be in error, which error words are subsequently corrected if possible using parity codes originally encoded into the signals prior to recording.

公开(公告)号：EP0098082A3

公开(公告)日：1986-05-07

申请号：EP83303488

申请日：1983-06-16

Applicant: SONY CORPORATION

Inventor： Creed, David Morris ,  Ive, John Goodwin Spencer

IPC: G11B05/09 ,  H04L01/10

CPC classification number: G11B20/1809

Abstract: @ A method of detecting and correcting errors in digital audio signals comprises assembling digital data words each of which corresponds to a digital audio signal representing an analog audio sample into units of six data words, assembling with each unit six redundant words derived by exclusive-OR operations on the data word in each row and each column of the unit, assembling the data words and redundant words into sub-blocks and adding cyclic redundancy check code words to the sub-block, recording and reproducing each sub-block, after reproduction using the code words of each sub-block to add error flags to each word in the sub-block, re-forming the units and assembling with each reproduced unit syndromes derived by exclusive-OR operations on the data words and redundant words in each row in each column of the unit, comparing the syndromes and correcting the error flags in dependence on this comparison, deriving horizontal syndromes by exclusive-OR operations on the data words and redundant words in each row of the reproduced unit and where there is only a single word in a row flagged as being in error, correcting that error word using the horizontal syndrome, and deriving vertical syndromes by exclusive-OR operations on the data words and the redundant word in each column of the reproduced unit and where there is only a single word in that column in error, correcting that error word using the vertical syndrome.

公开(公告)号：EP0131823A3

公开(公告)日：1985-11-06

申请号：EP84107581

申请日：1984-06-29

Applicant: Bauer, Norbert, Dr.-Ing.

Inventor： Bauer, Norbert, Dr.-Ing.

IPC: G11B05/09

CPC classification number: G11B20/1492 ,  G11B20/14

Abstract: Beschrieben wird eine Einrichtung zur Aufzeichnung binärer Signale auf einem magnetischen Informationsträger bei der an einem Aufzeichnungs-Magnetkopf bei jeder Ände rung der aufzuzeichnenden Signale von "0" auf "1" ein Nadel impuls der einen Polarität und bei jeder Änderung von "1" auf "0" ein Nadelimpuls der anderen Polarität angelegt wird.
Die Einrichtung weist entweder zwei Monoflops oder ein Monoflop auf.
Die Ausgangssignale der beiden Monoflops werden über eine Summationsschaltung am Magnetkopf angelegt, wahr end das Ausgangssignal des einen Monoflops über eine Logi kschaltung an den Magnetkopf angelegt wird, die die Stromr ichtung entsprechend dem anliegenden Datensignal umke hrt.
Weiter wird eine Einrichtung zur Rückgewinnung von auf einem magnetischen Informationsträger aufgezeichnet binä ren Signalen beschrieben, die den Nulldurchgang des Lesesi gnals ermittelt. Die Einrichtung weist drei Komparatoren auf, die das Lesesignal mit vorgegebenen Schwellenspannungen vergleichen. Nur wenn die Ausgangssignale der Komparato ren in einer bestimmten Reihenfolge auftreten, wird ein erhal tenes Signal als Lesesignal indentifiziert.

公开(公告)号：EP0084952A3

公开(公告)日：1985-06-26

申请号：EP83300265

申请日：1983-01-19

Applicant: SONY CORPORATION

Inventor： Watanabe, Tetsu c/o Patent Division ,  Tanaka, Masato c/o Patent Division

IPC: G11B05/09

CPC classification number: G11B20/1204 ,  G11B20/1202 ,  G11B20/1809 ,  G11B27/032 ,  G11B27/036 ,  G11B27/3027 ,  G11B27/36 ,  G11B2020/183

Abstract: Apparatus for recording a new digital signal in a track on a magnetic record medium which has a previously recorded digital signal in the track, the digital signal being arranged in data blocks each containing a sync signal, a data signal, an error correction code signal, and an error detection code signal, comprises reproducing means which reproduces each digital signal recorded on the magnetic record medium, a code generating means (8, 9) which supplies a discriminating code signal for each of the data blocks, and recording means (7, HR) which re-records the new digital signal and the respective discriminating code signals in the track on the magnetic record medium.

公开(公告)号：EP0084358A3

公开(公告)日：1985-01-09

申请号：EP83100299

申请日：1983-01-14

Applicant: TANDBERG DATA A/S

Inventor： Lia, Herman

IPC: G11B05/09 ,  H03K05/153

CPC classification number: G11B20/10212 ,  H03K5/1532

Abstract: Bei dem Verfahren werden die von einem Lesekopf (K) eines Magnetschichtspeichers abgegebenen Lesesignale (L) zunächst in an sich bekannter Weise verstärkt und differen ziert. Wenn die differenzierten Lesesignale (L2) in den Nulldurchgängen eine genügende Steigung aufweisen, wer den an den Nulldurchgängen Datenimpulse (D) erzeugt. Die Überprüfung der Steigung erfolgt durch eine nochmalige Differentation der differenzierten Lesesignale (L2) und durch eine Überprüfung, ob diese zweifach differenzierten Lesesig nale (L3) vorgegebene Schwellenspannungen (5) über- oder unterschreiten.

Abstract translation: 该方法包括以已知方式首先放大和微分由磁存储介质的读取头（K）发射的读取信号（L）。 如果差分读信号（L2）的斜率在它们交叉零的点处足够陡，则在过零点产生数据脉冲（D）。 通过差分读取信号（L2）的进一步分化以及通过检查这些两倍分辨的读取信号（L3）是否超过预定的阈值电压（S）来检查斜率。

公开(公告)号：EP0096109A3

公开(公告)日：1984-10-24

申请号：EP82109564

申请日：1982-10-15

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Nagumo, Masahide ,  Inagawa, June ,  Kojima, Tadashi

IPC: G06F11/10 ,  G11B05/09 ,  H04L01/10

CPC classification number: H03M13/151 ,  G06F7/724 ,  G06F7/726 ,  G11B20/1809

Abstract: An error correcting system uses an error location polynominal defined by double correction BCH codes each consisting of the elements of Galois field GF(2m), thereby to generate error locations σ 1 and σ 2 and error patterns e, and e 2 . The system has a first data processing system (401) for performing only additions and multiplications to generate error locations σ 1 and σ 2 and a second data processing system (402) for performing only additions and mutiplica- tions to generate error patterns e 1 and e 2 . The first data processing system (401) comprises a syndrome generator (41), a memory (43), an arithmetic logic unit (44), registers (45A) to (45C), latch circuits (46A) to (46F), registers (47A) to (47F), adder circuits (48A) and (48B) and a zero detector (49). The second data processing system (402) comprises a gate circuit (50), latch circuits (46H) and (46G), an arithmetic logic unit (44), registers (45A) to (45C) and a memory (43).