公开(公告)号：EP0096165A3

公开(公告)日：1984-10-17

申请号：EP83102308

申请日：1983-03-09

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Inagawa, Jun ,  Nagumo, Masahide ,  Kojima, Tadashi

IPC: G06F11/10 ,  G11B05/09 ,  H04L01/10

CPC classification number: G06F7/726 ,  G06F1/0307 ,  G11B20/1809 ,  H03M13/15

Abstract: Data representing one element α i of a Galois field GF(2 m ) are stored in a first linear shift register (52), and data representing another element α j of the Galois field GF(2 m ) are stored in a second linear shift register (53). 2 m elements of Galois field GF(2 m ) are divided into n groups. A table of the reciprocals of n elements located at specific positions respectively in n groups is stored in a converter (51) which includes a decoder (511) and an encoder (512). The data representing element α j are supplied from the second linear shift register (53) to the decoder (511). If the data representing the reciprocal of element α j are stored in the converter (51), they are read from the encoder (512). If they are not stored in the converter (51), the first linear shift register (52) and the second linear shift register (63) are shifted N times by control pulses generated by a NOR gate (NOR,) and an AND gate (AND, o ) until any one of the reciprocal data are read from the encoder (512), whereby the register (52) supplies data representing α i+N and the register (53) supplies data representing α -(j+N) . A multiplier (54) multiplies element α i by reciprocal α j or multiplies element α 1+N by reciprocal α -(j+N) , thereby performing the division: a i ÷ α j (= α i-j ).

公开(公告)号：EP0096163A3

公开(公告)日：1984-10-17

申请号：EP83102173

申请日：1983-03-05

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Inagawa, Jun ,  Nagumo, Masahide ,  Kojima, Tadashi

IPC: G06F11/10 ,  G11B05/09 ,  H04L01/10

CPC classification number: H03M13/15 ,  G06F7/726 ,  G11B20/1809

Abstract: An apparatus divides one element a' of a Galois field GF(2 m ) by another element α i of the field. Divider data α i are supplied to one of the first linear shift registers (A, to A4) and to the other first linear shift registers through α N1 , α N2 ,... multiplier circuits (51 to 53), respectively. Simultaneously, dividend data α i are supplied to one of the second linear shift registers (B, to B 4 ) and to the other second linear shift registers through α N1 , α N2 , ... multiplier circuits (58 to 60), respectively. "1" detector circuits (55 to 57) are connected to the outputs of the first linear shift registers (A, to A 4 ), respectively. The first linear shift registers (A, to A4) and the second linear shift registers (B 1 to B 4 ) are shifted several times until any "1" detector circuit (55 to 57) detects "1' in response to output signals from a 2-input AND gate (AND,,). When "1" is detected, a NOR gate (NOR, o ) supplies a signal of logical "0" to the AND gate (AND,,), whereby the AND gate (AND 11 ) stops supplying output signals. 2-input AND circuits (61 to 64) are connected at one input terminal to the outputs of the "1" detector circuits (54 to 57) and at the other input terminal to the outputs of the second linear shift registers (B, to B 4 ). The AND circuit connected to the "1" detector circuit supplies the data stored in the second linear shift register to which it is connected. The data representing the quotient of the division α i - a i , are delivered through an OR circuit (65).

公开(公告)号：EP0086659A3

公开(公告)日：1984-07-25

申请号：EP83300742

申请日：1983-02-15

Applicant: SONY CORPORATION

Inventor： Watanabe, Nobuhiko c/o Patent Division ,  Tanaka, Masato c/o Patent Division

IPC: G11B05/09 ,  G11B27/08 ,  G11B15/52

CPC classification number: G11B20/10527 ,  G11B15/52 ,  G11B19/28 ,  G11B20/1202 ,  G11B20/1204 ,  G11B20/18 ,  G11B27/032 ,  G11B27/10 ,  G11B2220/90 ,  G11B2220/913

Abstract: Apparatus for recording and reproducing a digital signal comprising successive data blocks, each data block including at least a plurality of data words and a block address which cycles with a predetermined phase relative to a reference signal and recorded on a recording medium (1) on which is also recorded a control signal in accordance with said reference signal, the apparatus comprising a head for reproducing the data words and block addresses within the data blocks from the recording medium (1), a time base corrector (15) for correcting a time base error contained in a reproduced data word, a head (HC) for reproducing the control signal from the recording medium (1), a counter (6) for generating a reference phase signal with a frequency of an integral multiple of more than twice the frequency of the control signal, a flip-flop circuit (5) for sampling the generated reference phase signal by the reproduced control signal so as to generate a phase compared output signal and a lock mode signal, and a servo loop (7 to 12) for controlling running of the recording medium (1) by the phase compared output signal.

公开(公告)号：EP0074644A3

公开(公告)日：1984-03-28

申请号：EP82108375

申请日：1982-09-10

Applicant: Hitachi, Ltd.

Inventor： Hoshino, Takashi ,  Arai, Takao ,  Nishimura, Keizo

IPC: G11B05/09 ,  G06F11/10 ,  H04L01/10

CPC classification number: G11B20/1809

Abstract: A PCM tape recording and reproducing apparatus for recording and reproducing an audio signal by using multi- track heads, comprises a frame interleaving device with a high dropout immunity function. The frame interleaving device comprises a distributor (10) for successively distributing continuous interleaved input data between tracks, within a multiplicity of tracks formed by splitting a magnetic tape, at a spacing of at least one track so that said continuous interleaved input data will not be shared between two continuous tracks in the same recording and reproducing direction, a data framing circuit (12) for forming a frame out of data to be distributed to each of said tracks and for applying said frame with a synchronization signal (2) at the top of said frame and with an error detection code (4) at the end of said frame, and a delay circuit (16, 20) for delaying data associated with a track by one frame or more with respect to data associated with a neighboring track in the same recording and reproducing as said track.

公开(公告)号：EP0083412A3

公开(公告)日：1983-11-09

申请号：EP82110817

申请日：1982-11-23

Applicant: International Business Machines Corporation

Inventor： Franaszek, Peter Anthony c/o IBM Corp.

IPC: G11B05/09

CPC classification number: G11B20/1426 ,  G06T9/005

Abstract: An algorithm and the hardware embodiment for producing a run lenght limited code useful in magnetic recording channels are described. The system described produces sequences which have a minimum of one zero and a maximum of seven zeros between adjacent 1's. The code is generated by a sequential scheme that maps two bits of unconstrained data into three bits of constrained data. The encoder is a finite state machine whose internal state description requires three bits. The encoder requires a looka- head of one future input vector (two bits) and a look back at the last channel bit generated during the immediately preceding encoding operation. The error propagation due to a random error is, at most, four bits in bursts of five. The hardware implementation is extremely simple and can operate at very high data speeds.

公开(公告)号：EP0071325A3

公开(公告)日：1983-06-15

申请号：EP82301906

申请日：1982-04-13

Applicant: CONTROL DATA CORPORATION

Inventor： Brown, Charles Albert

IPC: H04J15/00 ,  G11B05/09 ,  H04L05/00

CPC classification number: G11B20/10 ,  H04L5/04

Abstract: A method of demultiplexing a composite signal (c) containing a plurality of data streams (a, b), each stream being coded in a polarised code and phase shifted from other data streams by a predetermined phase shift comprises: providing a correlator signal (d, f) for each data stream (a, b), each correlator signal being mutually orthogonal with the or each other correlator signal and phase shifted from the other correlator signals by the predetermined phase shift of its corresponding data stream, and separately multiplying the composite signal by each correlator signal to derive resultant signals (e, g) each representing the data bits in a respective one of the data streams. There is also provided an apparatus for carrying out this method.

公开(公告)号：EP0047955A3

公开(公告)日：1982-10-13

申请号：EP81107028

申请日：1981-09-07

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Todokoro, Shigeru ,  Kojima, Tadashi

IPC: H03K05/08 ,  G11B05/09

Abstract: A wave-shaping circuit which comprises a comparator (12) for comparing the level of a signal reproduced from a magnetic tape on which, for example, PCM signals are recorded with the level of a reference signal, and a D flip-flop circuit (26) for holding an output signal from the comparator for a prescribed period. Where the reproduced signal has a higher level than the original level of the reference signal, then the reference signal is made to have a higher level than the original level by an output signal from the D flip-flop circuit (26), that is, an output signal from the comparator (12). Where the reproduced signal has a lower level than the original level of a reference signal, then the reference signal is made to have a lower level than the original level by the output signal from the comparator (12). As a result, strains occurring at the high density recording are not reproduced.

Abstract translation: 波形整形电路包括比较器（12）和D触发器电路（12），比较器（12）用于将从记录有例如PCM信号的磁带再现的信号的电平与参考信号的电平进行比较， 26），用于在规定的时间内保持来自比较器的输出信号。 在再现信号具有比参考信号的原始电平高的电平的情况下，通过来自D触发器电路（26）的输出信号使参考信号具有比原始电平更高的电平，即， 来自比较器（12）的输出信号。 在再现信号具有比参考信号的原始电平低的电平的情况下，通过来自比较器（12）的输出信号使参考信号具有比原始电平更低的电平。 结果，在高密度记录下出现的应变不被再现。

公开(公告)号：EP0052520A3

公开(公告)日：1982-06-30

申请号：EP81305444

申请日：1981-11-18

Applicant: SONY CORPORATION ,  KABUSHIKI KAISHA TOSHIBA

Inventor： Hoshimi, Susumo ,  Kojima, Tadashi

IPC: G11B27/02 ,  G11B05/09

CPC classification number: G11B5/09 ,  G11B27/032 ,  G11B27/323 ,  G11B2220/90

Abstract: A PCM signal processor having a signal input terminal which receives a PCM data signal from a PCM data signal reproducing apparatus such as a VTR (18R), a memory (14) for storing the PCM data signal, a standardized signal input terminal for providing a standardized signal corresponding to a synchronizing signal for synchronizing the VTR (18P), an address counter (38) for designating the address of the memory (14) which is to be read, and means for providing the address counter (38) with preset data in response to the standardized signal.

公开(公告)号：EP0052519A3

公开(公告)日：1982-06-23

申请号：EP81305443

申请日：1981-11-18

Applicant: SONY CORPORATION ,  KABUSHIKI KAISHA TOSHIBA

Inventor： Hoshimi, Susumu ,  Kojima, Tadashi

IPC: G11B05/09 ,  G06F11/10

CPC classification number: G11B5/86 ,  G11B27/032 ,  G11B2220/90 ,  G11B2220/913

Abstract: A pulse code modulation (PCM) signal recording system includes a first signal processor (1 to 7) for processing a recording signal into a predetermined PCM signal, a second signal processor (18 to 24) for processing a reproduced PCM signal into a recording signal, a first clock signal generator (9) generating a master clock signal, a second clock signal generator (12 to 14) generating at least one recording clock signal from the master clock signal, the recording clock signal being supplied to the first signal processor (1 to 7), a third clock signal generator (27) generating at least one reproducing clock signal from the master clock signal, the reproducing clock signal being supplied to the second signal processor (18 to 24), a comparator (32) digitally comparing the phases of the second and third clock signals and producing a control signal, and a controller (29) receiving the control signal and controlling the second or third clock signal so that they are synchronized.

公开(公告)号：EP0031499A3

公开(公告)日：1982-03-03

申请号：EP80107633

申请日：1980-12-04

Applicant: International Business Machines Corporation

Inventor： Brewer, James Arthur ,  Lowy, John Alfred

IPC: G06F11/10 ,  G06F11/16 ,  G11B05/09

CPC classification number: G06F11/1008 ,  G06F3/0601 ,  G06F11/1076 ,  G06F11/14 ,  G06F2003/0691

Abstract: To provide for a more economic buffer capacity through facilitating high speed readback check of data transferred to a cyclic memory (16) from a free input buffer before the source data is lost, the cyclic memory is organized into a number of data blocks, each interleaved with or simultaneously accessible with the other data blocks. Thus, a long data record comprises several data blocks and therefore several cycles of the memory. A readback check of data transferred is accomplished by writing data into one check number generator (51) and one data block in a first cycle, writing data into another block on the second cycle while reading back the first data block to a second check number generator (52), continuing in this manner until the entire record is transferred, and reading the last block of written data into the check number generator (52). The two generated check numbers are then compared to detect any error and effect a retransfer if required before the source of the record is lost by overwriting.

Abstract translation: 为了提供更经济的缓冲器容量，通过在源数据丢失之前便利于从空闲输入缓冲器传送到循环存储器（16）的数据的高速回读检查，循环存储器被组织成多个数据块，每个交错 与其他数据块同时访问。 因此，长数据记录包括几个数据块，因此包括存储器的几个周期。 通过将数据写入一个检查号码发生器（51）和一个数据块（在第一个周期内），将数据写入第二个周期的另一个数据块，同时将第一个数据块读回第二个检查号码生成器 （52），以这种方式继续，直到整个记录被传送，并且将最后的写入数据块读入检查号码发生器（52）。 然后将两个生成的检查号进行比较以检测任何错误，并且如果需要，则在重写之前通过重写丢失记录源。