公开(公告)号：US20180285233A1

公开(公告)日：2018-10-04

申请号：US15472932

申请日：2017-03-29

Applicant: Google Inc.

Inventor： Thomas Norrie ,  Naveen Kumar

IPC: G06F11/34 ,  G06F11/36 ,  G06F11/30 ,  G06F9/54

CPC classification number: G06F11/3466 ,  G06F9/542 ,  G06F11/302 ,  G06F11/348 ,  G06F11/3495 ,  G06F11/3612 ,  G06F2201/86 ,  G06F2201/865

Abstract: A computer-implemented method that includes monitoring execution of program code by first and second processor components. A computing system detects that a trigger condition is satisfied by: i) identifying an operand in a portion of the program code; or ii) determining that a current time of a clock of the computing system indicates a predefined time value. The operand and the predefined time value are used to initiate trace events. When the trigger condition is satisfied the system initiates trace events that generate trace data identifying respective hardware events occurring across the computing system. The system uses the trace data to generate a correlated set of trace data. The correlated trace data indicates a time ordered sequence of the respective hardware events. The system uses the correlated set of trace data to analyze performance of the executing program code.

公开(公告)号：US09875167B1

公开(公告)日：2018-01-23

申请号：US15473101

申请日：2017-03-29

Applicant: Google Inc.

Inventor： Thomas Norrie ,  Naveen Kumar

IPC: G06F15/16 ,  G06F11/30 ,  G06F11/36 ,  G06F9/54 ,  G06F11/34 ,  G06F17/30

CPC classification number: G06F11/302 ,  G06F9/542 ,  G06F11/3072 ,  G06F11/3075 ,  G06F11/3476 ,  G06F11/3495 ,  G06F11/3636 ,  G06F17/30044 ,  G06F2201/86 ,  G06F2201/865

Abstract: A computer-implemented method executed by one or more processors, the method includes monitoring execution of program code executed by a first processor component; and monitoring execution of program code executed by a second processor component. A computing system stores data identifying hardware events in a memory buffer. The stored events occur across processor units that include at least the first and second processor components. The hardware events each include an event time stamp and metadata characterizing the event. The system generates a data structure identifying the hardware events. The data structure arranges the events in a time ordered sequence and associates events with at least the first or second processor components. The system stores the data structure in a memory bank of a host device and uses the data structure to analyze performance of the program code executed by the first or second processor components.