公开(公告)号：US09747546B2

公开(公告)日：2017-08-29

申请号：US14844524

申请日：2015-09-03

Applicant: Google Inc.

Inventor： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC: G06N3/06 ,  G06N3/063 ,  G06F15/80

CPC classification number: G06N3/08 ,  G06F15/8046 ,  G06N3/063 ,  G06N5/04

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

公开(公告)号：US20180285233A1

公开(公告)日：2018-10-04

申请号：US15472932

申请日：2017-03-29

Applicant: Google Inc.

Inventor： Thomas Norrie ,  Naveen Kumar

IPC: G06F11/34 ,  G06F11/36 ,  G06F11/30 ,  G06F9/54

CPC classification number: G06F11/3466 ,  G06F9/542 ,  G06F11/302 ,  G06F11/348 ,  G06F11/3495 ,  G06F11/3612 ,  G06F2201/86 ,  G06F2201/865

Abstract: A computer-implemented method that includes monitoring execution of program code by first and second processor components. A computing system detects that a trigger condition is satisfied by: i) identifying an operand in a portion of the program code; or ii) determining that a current time of a clock of the computing system indicates a predefined time value. The operand and the predefined time value are used to initiate trace events. When the trigger condition is satisfied the system initiates trace events that generate trace data identifying respective hardware events occurring across the computing system. The system uses the trace data to generate a correlated set of trace data. The correlated trace data indicates a time ordered sequence of the respective hardware events. The system uses the correlated set of trace data to analyze performance of the executing program code.

公开(公告)号：US20180260220A1

公开(公告)日：2018-09-13

申请号：US15454214

申请日：2017-03-09

Applicant: Google Inc.

Inventor： William Lacy ,  Gregory Michael Thorson ,  Christopher Aaron Clark ,  Norman Paul Jouppi ,  Thomas Norrie ,  Andrew Everett Phelps

IPC: G06F9/30 ,  G06F13/40 ,  G06F13/36 ,  G06F13/42 ,  G06F15/80 ,  G06F17/16 ,  G06F7/58

CPC classification number: G06F9/3001 ,  G06F7/588 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F13/36 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/8046 ,  G06F15/8053 ,  G06F15/8092 ,  G06F17/16 ,  G06N3/063

Abstract: A vector processing unit is described, and includes processor units that each include multiple processing resources. The processor units are each configured to perform arithmetic operations associated with vectorized computations. The vector processing unit includes a vector memory in data communication with each of the processor units and their respective processing resources. The vector memory includes memory banks configured to store data used by each of the processor units to perform the arithmetic operations. The processor units and the vector memory are tightly coupled within an area of the vector processing unit such that data communications are exchanged at a high bandwidth based on the placement of respective processor units relative to one another, and based on the placement of the vector memory relative to each processor unit.

公开(公告)号：US20180046907A1

公开(公告)日：2018-02-15

申请号：US15686615

申请日：2017-08-25

Applicant: Google Inc.

Inventor： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC: G06N3/063 ,  G06F15/80

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

公开(公告)号：US09710748B2

公开(公告)日：2017-07-18

申请号：US15389202

申请日：2016-12-22

Applicant: Google Inc.

Inventor： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC: G06N3/08 ,  G06N5/04

CPC classification number: G06N3/08 ,  G06F15/8046 ,  G06N3/063 ,  G06N5/04

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

公开(公告)号：US09875167B1

公开(公告)日：2018-01-23

申请号：US15473101

申请日：2017-03-29

Applicant: Google Inc.

Inventor： Thomas Norrie ,  Naveen Kumar

IPC: G06F15/16 ,  G06F11/30 ,  G06F11/36 ,  G06F9/54 ,  G06F11/34 ,  G06F17/30

CPC classification number: G06F11/302 ,  G06F9/542 ,  G06F11/3072 ,  G06F11/3075 ,  G06F11/3476 ,  G06F11/3495 ,  G06F11/3636 ,  G06F17/30044 ,  G06F2201/86 ,  G06F2201/865

Abstract: A computer-implemented method executed by one or more processors, the method includes monitoring execution of program code executed by a first processor component; and monitoring execution of program code executed by a second processor component. A computing system stores data identifying hardware events in a memory buffer. The stored events occur across processor units that include at least the first and second processor components. The hardware events each include an event time stamp and metadata characterizing the event. The system generates a data structure identifying the hardware events. The data structure arranges the events in a time ordered sequence and associates events with at least the first or second processor components. The system stores the data structure in a memory bank of a host device and uses the data structure to analyze performance of the program code executed by the first or second processor components.

公开(公告)号：US20170103313A1

公开(公告)日：2017-04-13

申请号：US15389202

申请日：2016-12-22

Applicant: Google Inc.

Inventor： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC: G06N3/08 ,  G06N5/04

CPC classification number: G06N3/08 ,  G06F15/8046 ,  G06N3/063 ,  G06N5/04

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

公开(公告)号：US20160342891A1

公开(公告)日：2016-11-24

申请号：US14844524

申请日：2015-09-03

Applicant: Google Inc.

Inventor： Jonathan Ross ,  Norman Paul Jouppi ,  Andrew Everett Phelps ,  Reginald Clifford Young ,  Thomas Norrie ,  Gregory Michael Thorson ,  Dan Luu

IPC: G06N3/08 ,  G06N99/00

CPC classification number: G06N3/08 ,  G06F15/8046 ,  G06N3/063 ,  G06N5/04

Abstract: A circuit for performing neural network computations for a neural network comprising a plurality of neural network layers, the circuit comprising: a matrix computation unit configured to, for each of the plurality of neural network layers: receive a plurality of weight inputs and a plurality of activation inputs for the neural network layer, and generate a plurality of accumulated values based on the plurality of weight inputs and the plurality of activation inputs; and a vector computation unit communicatively coupled to the matrix computation unit and configured to, for each of the plurality of neural network layers: apply an activation function to each accumulated value generated by the matrix computation unit to generate a plurality of activated values for the neural network layer.

Abstract translation: 一种用于对包括多个神经网络层的神经网络执行神经网络计算的电路，所述电路包括：矩阵计算单元，被配置为针对所述多个神经网络层中的每个神经网络层：接收多个权重输入和多个 用于所述神经网络层的激活输入，并且基于所述多个权重输入和所述多个激活输入生成多个累积值; 以及矢量计算单元，其通信地耦合到所述矩阵计算单元，并且被配置为针对所述多个神经网络层中的每个神经网络层：将激活函数应用于由所述矩阵计算单元生成的每个累积值，以生成所述神经元的多个激活值 网络层。