PRINTED WIRING BOARD
    1.
    发明申请

    公开(公告)号:US20240431031A1

    公开(公告)日:2024-12-26

    申请号:US18748790

    申请日:2024-06-20

    Abstract: A printed wiring board includes a first insulating layer, a connection conductor layer including wiring, a second insulating layer covering the connection conductor layer, a conductor layer including first and second electrodes such that the first electrode mounts a first electronic component and the second electrode mounts a second electronic component, and via conductors including first and second via conductors. The first via conductor connects the first electrode and wiring. The second via conductor connects the second electrode and wiring. The conductor layer includes a seed layer and an electrolytic plating layer. The seed layer includes a first layer formed on the first insulating layer and a second layer formed on the first layer, a width of the first layer is larger than a width of the second layer, and a width of the electrolytic plating layer is larger than the width of the first layer of the seed layer.

    PRINTED WIRING BOARD
    2.
    发明公开

    公开(公告)号:US20230319987A1

    公开(公告)日:2023-10-05

    申请号:US18191062

    申请日:2023-03-28

    Abstract: A printed wiring board includes a first conductor layer, an insulating layer formed on the first conductor layer, a second conductor layer formed on a surface of the insulating layer and including a conductor circuit, and a via conductor formed in an opening formed in the insulating layer and connecting the first and second conductor layers. The second conductor layer and via conductor include a seed layer and an electrolytic plating layer formed on the seed layer such that the seed layer has a first layer and a second layer formed on the first layer, the first layer has a width greater than a width of the second layer in cross section of the conductor circuit in the second conductor layer and that the electrolytic plating layer has a width greater than the width of the first layer in cross section of the conductor circuit in the second conductor layer.

    PRINTED WIRING BOARD
    3.
    发明公开

    公开(公告)号:US20240260179A1

    公开(公告)日:2024-08-01

    申请号:US18426547

    申请日:2024-01-30

    Abstract: A printed wiring board includes a conductor layer, an outermost insulating layer formed on the conductor layer and having an opening exposing a portion of the conductor layer, and a metal post formed in the opening of the outermost insulating layer and including a seed layer and an electrolytic plating layer formed on the seed layer such that the metal post has a height exceeding a surface of the outermost insulating layer and has a portion exceeding a height of the outermost insulating layer, the seed layer of the metal post has a first layer and a second layer formed on the first layer. The portion exceeding the height of the outermost insulating layer is formed such that a width of the first layer is larger than a width of the second layer, and a width of the electrolytic plating layer is larger than the width of the first layer.

    WIRING SUBSTRATE
    4.
    发明公开
    WIRING SUBSTRATE 审中-公开

    公开(公告)号:US20240339388A1

    公开(公告)日:2024-10-10

    申请号:US18626736

    申请日:2024-04-04

    Abstract: A wiring substrate includes a first build-up part including an insulating layer and a conductor layer, and a second build-up part including an insulating layer and a conductor layer. The minimum wiring width of wirings in the conductor layer of the first build-up part is smaller than the minimum wiring width of wirings in the conductor layer of the second build-up part. The minimum inter-wiring distance of the wirings in the first part is smaller than the minimum inter-wiring distance of the wirings in the second part. The first build-up part is formed such that the conductor layer includes a conductor pattern including a first metal layer, a second metal layer, and a third metal layer. The width of the first metal layer is larger than the width of the second metal layer. The width of the third metal layer is larger than the width of the first metal layer.

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