公开(公告)号：US20160259646A1

公开(公告)日：2016-09-08

申请号：US15155204

申请日：2016-05-16

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Michael W. Chynoweth ,  Ofer Levy ,  Jason W. Brandt ,  Angela Schmid

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/30098 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/865 ,  G06F2201/88

Abstract: A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device. The processing device further includes at least one register communicably coupled to the LBR counter, the at least one register to provide an LBR structure comprising a plurality of LBR entries. An LBR entry of the plurality of LBR entries includes an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter in response to creation of the LBR entry.

Abstract translation: 公开了一种在最后的分支记录（LBR）中实现经过周期定时器的处理装置。 本公开的处理装置包括与处理装置的每个周期重复的最后一个分支记录（LBR）计数器。 所述处理设备还包括至少一个可通信地耦合到所述LBR计数器的寄存器，所述至少一个寄存器提供包括多个LBR入口的LBR结构。 多个LBR条目的LBR条目包括由处理装置执行的分支指令的地址指令指针（IP），分支指令的目标的地址IP以及存储LBR的值的经过时间字段 反对创建LBR条目。

公开(公告)号：US20230315470A1

公开(公告)日：2023-10-05

申请号：US17708933

申请日：2022-03-30

Applicant: Intel Corporation

Inventor： Matthew Merten ,  Beeman Strong ,  Moshe Cohen ,  Ahmad Yasin ,  Andreas Kleen ,  Stanislav Bratanov ,  Karthik Gopalakrishnan ,  Angela Schmid ,  Grant Zhou

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32 ,  G06F11/34

CPC classification number: G06F9/3814 ,  G06F9/30101 ,  G06F9/321 ,  G06F11/3409

Abstract: Techniques and mechanisms for configuring processor event-based sampling (PEBS) with a set of control registers. In an embodiment, a first control register of a processor is programmed to store a physical address of a location in a buffer which receives PEBS records. The first control register is further programmed or otherwise configured to store an indication of a size of the buffer. A second control register of the processor stores a physical address of a location in the buffer were a next PEBS record is to be stored. In another embodiment, the processor further comprises multiple control registers which variously configure PEBS generation on a per-counter basis.

公开(公告)号：US09342433B2

公开(公告)日：2016-05-17

申请号：US13922421

申请日：2013-06-20

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Michael W. Chynoweth ,  Ofer Levy ,  Jason W. Brandt ,  Angela Schmid

IPC: G06F9/30 ,  G06F11/34

CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/30098 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/865 ,  G06F2201/88

Abstract: A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device and an LBR structure communicably coupled to the LBR counter. The LBR structure comprises a plurality of LBR entries. Furthermore, an LBR entry of the plurality of LBR entries comprises an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter when the LBR entry is created.

Abstract translation: 公开了一种在最后的分支记录（LBR）中实现经过周期定时器的处理装置。 本公开的处理装置包括与处理装置的每个周期重复的最后一个分支记录（LBR）计数器和可通信地耦合到LBR计数器的LBR结构。 LBR结构包括多个LBR条目。 此外，多个LBR条目的LBR条目包括由处理装置执行的分支指令的地址指令指针（IP），分支指令的目标的地址IP以及存储分支指令的值的经过时间字段 当创建LBR条目时，LBR计数器。

公开(公告)号：US09690588B2

公开(公告)日：2017-06-27

申请号：US15155204

申请日：2016-05-16

Applicant: Intel Corporation

Inventor： Ahmad Yasin ,  Michael W. Chynoweth ,  Ofer Levy ,  Jason W. Brandt ,  Angela Schmid

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/34

CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/30098 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/865 ,  G06F2201/88

Abstract: A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device. The processing device further includes at least one register communicably coupled to the LBR counter, the at least one register to provide an LBR structure comprising a plurality of LBR entries. An LBR entry of the plurality of LBR entries includes an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter in response to creation of the LBR entry.