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    Thread pause processors, methods, systems, and instructions
    2.
    发明授权
    Thread pause processors, methods, systems, and instructions 有权

    公开(公告)号：US10467011B2

    公开(公告)日：2019-11-05

    申请号：US14336596

    申请日：2014-07-21

    Applicant: Intel Corporation

    Inventor： Lihu Rappoport ,  Zeev Sperber ,  Michael Mishaeli ,  Stanislav Shwartsman ,  Lev Makovsky ,  Adi Yoaz ,  Ofer Levy

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A processor of an aspect includes a decode unit to decode a thread pause instruction from a first thread. A back-end portion of the processor is coupled with the decode unit. The back-end portion of the processor, in response to the thread pause instruction, is to pause processing of subsequent instructions of the first thread for execution. The subsequent instructions occur after the thread pause instruction in program order. The back-end portion, in response to the thread pause instruction, is also to keep at least a majority of the back-end portion of the processor, empty of instructions of the first thread, except for the thread pause instruction, for a predetermined period of time. The majority may include a plurality of execution units and an instruction queue unit.

    Elapsed cycle timer in last branch records
    4.
    发明授权
    Elapsed cycle timer in last branch records 有权
    最后一个分支记录中的循环计时器

    公开(公告)号：US09342433B2

    公开(公告)日：2016-05-17

    申请号：US13922421

    申请日：2013-06-20

    Applicant: Intel Corporation

    Inventor： Ahmad Yasin ,  Michael W. Chynoweth ,  Ofer Levy ,  Jason W. Brandt ,  Angela Schmid

    IPC: G06F9/30 ,  G06F11/34

    CPC classification number: G06F9/3806 ,  G06F9/30058 ,  G06F9/30098 ,  G06F11/3419 ,  G06F11/348 ,  G06F2201/865 ,  G06F2201/88

    Abstract: A processing device implementing an elapsed cycle timer in last branch records (LBRs) is disclosed. A processing device of the disclosure includes a last branch record (LBR) counter to iterate with each cycle of the processing device and an LBR structure communicably coupled to the LBR counter. The LBR structure comprises a plurality of LBR entries. Furthermore, an LBR entry of the plurality of LBR entries comprises an address instruction pointer (IP) of a branch instruction executed by the processing device, an address IP of a target of the branch instruction, and an elapsed time field that stores a value of the LBR counter when the LBR entry is created.

    Abstract translation: 公开了一种在最后的分支记录（LBR）中实现经过周期定时器的处理装置。 本公开的处理装置包括与处理装置的每个周期重复的最后一个分支记录（LBR）计数器和可通信地耦合到LBR计数器的LBR结构。 LBR结构包括多个LBR条目。 此外，多个LBR条目的LBR条目包括由处理装置执行的分支指令的地址指令指针（IP），分支指令的目标的地址IP以及存储分支指令的值的经过时间字段 当创建LBR条目时，LBR计数器。

    THREAD PAUSE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
    5.
    发明申请
    THREAD PAUSE PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
    线程暂停处理器，方法，系统和指令

    公开(公告)号：US20160019063A1

    公开(公告)日：2016-01-21

    申请号：US14336596

    申请日：2014-07-21

    Applicant: Intel Corporation

    Inventor： Lihu Rappoport ,  Zeev Sperber ,  Michael Mishaeli ,  Stanislav Shwartsman ,  Lev Makovsky ,  Adi Yoaz ,  Ofer Levy

    IPC: G06F9/30

    CPC classification number: G06F9/3851 ,  G06F9/30 ,  G06F9/30058 ,  G06F9/3009

    Abstract: A processor of an aspect includes a decode unit to decode a thread pause instruction from a first thread. A back-end portion of the processor is coupled with the decode unit. The back-end portion of the processor, in response to the thread pause instruction, is to pause processing of subsequent instructions of the first thread for execution. The subsequent instructions occur after the thread pause instruction in program order. The back-end portion, in response to the thread pause instruction, is also to keep at least a majority of the back-end portion of the processor, empty of instructions of the first thread, except for the thread pause instruction, for a predetermined period of time. The majority may include a plurality of execution units and an instruction queue unit.

    Abstract translation: 一个方面的处理器包括解码单元，用于对来自第一线程的线程暂停指令进行解码。 处理器的后端部分与解码单元耦合。 响应于线程暂停指令，处理器的后端部分是暂停用于执行的第一线程的后续指令的处理。 随后的指令以程序顺序发生在线程暂停指令之后。 响应于线程暂停指令，后端部分还将保持处理器的后端部分的至少大部分，除了线程暂停指令之外的第一线程的指令，预定的 一段的时间。 大多数可以包括多个执行单元和指令队列单元。

    Tracking mode of a processing device in instruction tracing systems
    8.
    发明授权
    Tracking mode of a processing device in instruction tracing systems 有权

    公开(公告)号：US10331452B2

    公开(公告)日：2019-06-25

    申请号：US14126313

    申请日：2013-06-27

    Applicant: Intel Corporation

    Inventor： Thilo Schmitt ,  Peter Lachner ,  Beeman Strong ,  Ofer Levy ,  Thomas Toll ,  Matthew Merten ,  Tong Li ,  Ravi Rajwar ,  Konrad Lai

    IPC: G06F9/30 ,  G06F11/36

    Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for tracking the mode of processing devices in an instruction tracing system. The method may include receiving an indication of a change in a current execution mode of the processing device. The method may also include determining that the current execution mode of the received indication is different than a value of an execution mode of a first execution mode (EM) packet previously-generated by the IT module. The method may also include generating, based on the determining that the current execution mode is different, a second EM packet that provides a value of the current execution mode of the processing device to indicate the change in the execution mode for an instruction in a trace generated by the IT module. The method may further include generating transactional memory (TMX) packets having n bit mode pattern in the packet log. The n is at least two and the n bit mode indicates transaction status of the TMX operation.

    Method and Logic for Maintaining Performance Counters with Dynamic Frequencies
    9.
    发明申请
    Method and Logic for Maintaining Performance Counters with Dynamic Frequencies 审中-公开

    公开(公告)号：US20180004532A1

    公开(公告)日：2018-01-04

    申请号：US15200326

    申请日：2016-07-01

    Applicant: Intel Corporation

    Inventor： Ahmad Yasin ,  Eti Pardo-Fridman ,  Ofer Levy

    IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0875

    Abstract: A processor includes a front end including circuitry to decode an instruction from an instruction stream and a core including circuitry to process the instruction. The core includes an execution pipeline, a dynamic core frequency logic unit, and a counter compensation logic unit. The execution pipeline includes circuitry to execute the instruction. The dynamic core frequency logic unit includes circuitry to squash a clock of the core to reduce a core frequency. The clock may not be visible to software. The counter compensation logic unit includes circuitry to adjust a performance counter increment associated with a performance counter based on at least the dynamic core frequency logic unit circuitry to squash a clock of the core to reduce a core frequency.

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