公开(公告)号：US20220199771A1

公开(公告)日：2022-06-23

申请号：US17133092

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Jack T. KAVALIEROS ,  Stephen M. CEA ,  Ashish AGRAWAL ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

Abstract: Neighboring gate-all-around integrated circuit structures having a conductive contact stressor between epitaxial source or drain regions are described. In an example, a first vertical arrangement of nanowires and a second vertical arrangement of nanowires above a substrate. A first gate stack is over the first vertical arrangement of nanowires. A second gate stack is over the second vertical arrangement of nanowires. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening conductive contact structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures. The intervening conductive contact structure imparts a stress to the neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.

公开(公告)号：US20220190159A1

公开(公告)日：2022-06-16

申请号：US17122907

申请日：2020-12-15

Applicant: Intel Corporation

Inventor： Rajat PAUL ,  Willy RACHMADY ,  Jessica TORRES ,  Rambert NAHM ,  Ashish AGRAWAL ,  Siddharth CHOUKSEY ,  Gilbert DEWEY ,  Jack T. KAVALIEROS

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/167 ,  H01L29/165 ,  H01L29/66 ,  H01L27/12

Abstract: Integrated circuit structures having GeSnB source or drain structures, and methods of fabricating integrated circuit structures having GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires. The first and second epitaxial source or drain structures include germanium, tin and boron.

公开(公告)号：US20210351105A1

公开(公告)日：2021-11-11

申请号：US17303270

申请日：2021-05-25

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish AGRAWAL ,  Urusa ALAAN ,  Christopher JEZEWSKI ,  Mauro KOBRINSKY ,  Kevin LIN ,  Abhishek Anil SHARMA

IPC: H01L23/40 ,  H01L21/70 ,  H01L21/822 ,  H01L27/12 ,  H01L23/532

Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

公开(公告)号：US20220109072A1

公开(公告)日：2022-04-07

申请号：US17546002

申请日：2021-12-08

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Jack T. KAVALIEROS ,  Seung Hoon SUNG ,  Siddharth CHOUKSEY ,  Harold W. KENNEL ,  Dipanjan BASU ,  Ashish AGRAWAL ,  Glenn A. GLASS ,  Tahir GHANI ,  Anand S. MURTHY

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/205 ,  H01L29/08 ,  H01L29/165

Abstract: Integrated circuit transistor structures are disclosed that reduce band-to-band tunneling between the channel region and the source/drain region of the transistor, without adversely increasing the extrinsic resistance of the device. In an example embodiment, the structure includes one or more spacer configured to separate the source and/or drain from the channel region. The spacer(s) regions comprise a semiconductor material that provides a relatively high conduction band offset (CBO) and a relatively low valence band offset (VBO) for PMOS devices, and a relatively high VBO and a relatively low CBO for NMOS devices. In some cases, the spacer includes silicon, germanium, and carbon (e.g., for devices having germanium channel). The proportions may be at least 10% silicon by atomic percentage, at least 85% germanium by atomic percentage, and at least 1% carbon by atomic percentage. Other embodiments are implemented with III-V materials.

公开(公告)号：US20190140061A1

公开(公告)日：2019-05-09

申请号：US16094151

申请日：2016-06-27

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Van H. LE ,  Jack T. KAVALIEROS ,  Willy RACHMADY ,  Matthew V. METZ ,  Ashish AGRAWAL ,  Seung Hoon SUNG

IPC: H01L29/417 ,  H01L29/78 ,  H01L21/768

Abstract: An interlayer film is deposited on a device layer on a substrate. A contact layer is deposited on the interlayer film. The interlayer film has a broken bandgap alignment to the device layer to reduce a contact resistance of the contact layer to the device layer.

公开(公告)号：US20180366587A1

公开(公告)日：2018-12-20

申请号：US15777117

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC ,  Kent E. MILLARD ,  Marc C. FRENCH ,  Ashish AGRAWAL ,  Benjamin CHU-KUNG ,  Ryan E. ARCH

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L29/40 ,  H01L29/66

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

公开(公告)号：US20180331195A1

公开(公告)日：2018-11-15

申请号：US15773894

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Benjamin CHU-KUNG ,  Van H. LE ,  Gilbert DEWEY ,  Ashish AGRAWAL ,  Jack T. KAVALIEROS

IPC: H01L29/47 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/47 ,  H01L21/28255 ,  H01L29/45 ,  H01L29/66477 ,  H01L29/78

Abstract: An apparatus including a substrate; a transistor device on the substrate including a channel and a source and a drain disposed between the channel; a source contact coupled to the source and a drain contact coupled to the drain; and the source and drain each including a composition including a concentration of germanium at an interface with the channel that is greater than a concentration of germanium at a junction with the source contact. A method including defining an area on a substrate for a transistor device; forming a source and a drain each including an interface with the channel; and forming a contact to one of the source and the drain, wherein a composition of each of the source and the drain includes a concentration of germanium at an interface with the channel that is greater than a concentration at a junction with the contact.

公开(公告)号：US20220148917A1

公开(公告)日：2022-05-12

申请号：US17648821

申请日：2022-01-25

Applicant: Intel Corporation

Inventor： Carl NAYLOR ,  Ashish AGRAWAL ,  Kevin LIN ,  Abhishek Anil SHARMA ,  Mauro KOBRINSKY ,  Christopher JEZEWSKI ,  Urusa ALAAN

IPC: H01L21/768 ,  H01L21/683 ,  H01L23/532

Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.

公开(公告)号：US20200006492A1

公开(公告)日：2020-01-02

申请号：US16022510

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： Siddharth CHOUKSEY ,  Glenn GLASS ,  Anand MURTHY ,  Harold KENNEL ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Ashish AGRAWAL ,  Seung Hoon SUNG

IPC: H01L29/165 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US20190122972A1

公开(公告)日：2019-04-25

申请号：US16094817

申请日：2016-06-29

Applicant: Intel Corporation

Inventor： Benjamin CHU-KUNG ,  Van H. LE ,  Willy RACHMADY ,  Matthew V. METZ ,  Jack T. KAVALIEROS ,  Ashish AGRAWAL ,  Seung Hoon SUNG

IPC: H01L23/498 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: A subfin layer is deposited on a substrate. A fin layer is deposited on the subfin layer. The subfin layer has a conduction band energy offset relative to the fin layer to prevent a leakage in the subfin layer. In one embodiment, the subfin layer comprises a group IV semiconductor material layer that has a bandgap greater than a bandgap of the fin layer.