公开(公告)号：US20200185226A1

公开(公告)日：2020-06-11

申请号：US16334324

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Rahim KASIM ,  Manish CHANDHOK ,  Florian Gstrein

IPC: H01L21/302 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member. Such a metallized semiconductor die can be further processed according to a process of record until metallization, after which additional selective removal of another amount of metal can be implemented. Semiconductor dies having neighboring metal interconnects separated by backfilled dielectric regions also are provided.

公开(公告)号：US20190267961A1

公开(公告)日：2019-08-29

申请号：US16348830

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Kimin JUN ,  Edris MOHAMMED

IPC: H03H3/02 ,  H03H9/17

Abstract: The RF filters used in conventional mobile devices often include resonator structures, which often require free-standing air-gap structure to prevent mechanical vibrations of the resonator from being damped by a bulk material. A method for fabricating a resonator structure comprises depositing a non-conformal thin-film to the resonator structure to seal air gap cavities in the resonator structure.

公开(公告)号：US20180158694A1

公开(公告)日：2018-06-07

申请号：US15575283

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert Lindsey BRISTOL ,  Alan M. MYERS

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/32139 ,  H01L21/0337 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L2224/16225

Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.

公开(公告)号：US20160245841A1

公开(公告)日：2016-08-25

申请号：US15051856

申请日：2016-02-24

Applicant: Intel Corporation

Inventor： Qing MA ,  Valluri RAO ,  Feras EID ,  Kevin LIN ,  Weng Hong TEH ,  Johanna SWAN ,  Robert SANKMAN

IPC: G01P15/097

CPC classification number: G01P15/097 ,  G01P15/105 ,  G01P15/18

Abstract: An accelerometer includes a mass, suspended by a beam, and associated conductive paths. Each conductive path is subjected to a magnetic field, such that, when a time varying signal is applied to the conductive paths, a characteristic resonant frequency is produced, and when the mass experiences an acceleration, a respective change in the resonant frequency is produced that may be interpreted as acceleration data. Embodiments include methods of manufacturing an accelerometer and systems and devices incorporating the accelerometer.

Abstract translation: 加速度计包括由梁悬挂的质量块和相关联的导电路径。 每个导电路径受到磁场的影响，使得当对导电路径施加时变信号时，产生特性谐振频率，并且当质量经历加速度时，产生谐振频率的相应变化， 可以解释为加速度数据。 实施例包括制造加速度计的方法和结合有加速度计的系统和装置。

公开(公告)号：US20210351105A1

公开(公告)日：2021-11-11

申请号：US17303270

申请日：2021-05-25

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Ashish AGRAWAL ,  Urusa ALAAN ,  Christopher JEZEWSKI ,  Mauro KOBRINSKY ,  Kevin LIN ,  Abhishek Anil SHARMA

IPC: H01L23/40 ,  H01L21/70 ,  H01L21/822 ,  H01L27/12 ,  H01L23/532

Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.

公开(公告)号：US20210005511A1

公开(公告)日：2021-01-07

申请号：US17025087

申请日：2020-09-18

Applicant: Intel Corporation

Inventor： Kevin LIN ,  Robert L. BRISTOL ,  Richard E. SCHENKER

IPC: H01L21/768 ,  H01L23/528 ,  H01L21/033

Abstract: Damascene plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer. The conductive tab couples two of the plurality of conductive lines along a second direction orthogonal to the first direction.

公开(公告)号：US20190393147A1

公开(公告)日：2019-12-26

申请号：US16017962

申请日：2018-06-25

Applicant: Intel Corporation

Inventor： Kevin LIN

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

Abstract: An integrated circuit structure comprises a first and second conductive structures formed in an interlayer dielectric (ILD) of a metallization stack over a substrate. The first conductive structure comprises a first conductive line, and first dummy structures located adjacent to one or more sides of the first conductive line, wherein the first dummy structures comprise respective arrays of dielectric core segments having a Young's modulus larger than the Young's modulus of the ILD, the dielectric core segments being approximately 1-3 microns in width and spaced apart by approximately 1-3 microns. The second conductive structure formed in the ILD comprises a conductive surface and second dummy structures formed in the conductive surface, where the second dummy structures comprising an array of conductive pillars.

公开(公告)号：US20170158501A1

公开(公告)日：2017-06-08

申请号：US15301337

申请日：2014-06-27

Applicant: Intel Corporation

Inventor： Jorge A. MUNOZ ,  Dmitri E. NIKONOV ,  Kelin J. KUHN ,  Patrick THEOFANIS ,  Chytra PAWASHE ,  Kevin LIN ,  Seiyon KIM

IPC: B82B1/00 ,  H01H59/00 ,  B82B3/00 ,  H01L29/66 ,  H01L29/84 ,  H01L29/82

CPC classification number: B82B1/005 ,  B81B3/0016 ,  B81B7/02 ,  B81B2201/014 ,  B81B2203/0118 ,  B82B1/002 ,  B82B3/0023 ,  B82Y15/00 ,  B82Y25/00 ,  B82Y40/00 ,  H01H1/0094 ,  H01H1/54 ,  H01H59/0009 ,  H01L29/66227 ,  H01L29/82 ,  H01L29/84 ,  Y10S977/732 ,  Y10S977/838 ,  Y10S977/888 ,  Y10S977/938

Abstract: Nanoelectromechanical (NEMS) devices having nanomagnets for an improved range of operating voltages and improved control of dimensions of a cantilever are described. For example, in an embodiment, a nanoelectromechanical (NEMS) device includes a substrate layer, a first magnetic layer disposed above the substrate layer, a first dielectric layer disposed above the first magnetic layer, a second dielectric disposed above the first dielectric layer, and a cantilever disposed above the second dielectric layer. The cantilever bends from a first position to a second position towards the substrate layer when a voltage is applied to the cantilever.

公开(公告)号：US20200303238A1

公开(公告)日：2020-09-24

申请号：US16358520

申请日：2019-03-19

Applicant: Intel Corporation

Inventor： Ehren MANNEBACH ,  Aaron LILAK ,  Rishabh MEHANDRU ,  Hui Jae YOO ,  Patrick MORROW ,  Kevin LIN

IPC: H01L21/768 ,  H01L29/417 ,  H01L21/762 ,  H01L21/683 ,  H01L23/31

Abstract: Embodiments herein describe techniques for a semiconductor device including a carrier wafer, and an integrated circuit (IC) formed on a device wafer bonded to the carrier wafer. The IC includes a front end layer having one or more transistors at front end of the device wafer, and a back end layer having a metal interconnect coupled to the one or more transistors. One or more gaps may be formed by removing components of the one or more transistors. Furthermore, the IC includes a capping layer at backside of the device wafer next to the front end layer of the device wafer, filling at least partially the one or more gaps of the front end layer. Moreover, the IC includes one or more air gaps formed within the one or more gaps, and between the capping layer and the back end layer. Other embodiments may be described and/or claimed.

公开(公告)号：US20200066521A1

公开(公告)日：2020-02-27

申请号：US16489331

申请日：2017-03-31

Applicant: INTEL CORPORATION

Inventor： Kevin LIN ,  Rami HOURANI ,  Elliot N. TAN ,  Manish CHANDHOK ,  Anant H. JAHAGIRDAR ,  Robert L. BRISTOL ,  Richard E. SCHENKER ,  Aaron Douglas LILAK

IPC: H01L21/033 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3115

Abstract: A computing device including tight pitch features and a method of fabricating a computing device using colored spacer formation is disclosed. The computing device includes a memory and an integrated circuit coupled to the memory. The integrated circuit includes a first multitude of features above a substrate. The integrated circuit die includes a second multitude of features above the substrate. The first multitude of features and the second multitude of features are same features disposed in a first direction. The first multitude of features interleave with the second multitude of features. The first multitude of features has a first size and the second multitude of features has a second size.